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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9220 датащи(PDF) 73 Page - Microchip Technology |
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LAN9220 датащи(HTML) 73 Page - Microchip Technology |
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73 / 142 page  2006-2017 Microchip Technology Inc. DS00002417A-page 73 LAN9220 5.3.5 BYTE_TEST—BYTE ORDER TEST REGISTER This register can be used to determine the byte ordering of the current configuration 5.3.6 FIFO_INT—FIFO LEVEL INTERRUPTS This register configures the limits where the FIFO Controllers will generate system interrupts. Offset: 64h Size: 32 bits Bits Description Type Default 31:0 Byte Test RO 87654321h Offset: 68h Size: 32 bits Bits Description Type Default 31-24 TX Data Available Level. The value in this field sets the level, in number of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be generated. When the TX data FIFO free space is greater than this value a TX FIFO Available interrupt (TDFA) will be generated. R/W 48h 23-16 TX Status Level. The value in this field sets the level, in number of DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be generated. When the TX Status FIFO used space is greater than this value an TX Status FIFO Level interrupt (TSFL) will be generated. R/W 00h 15-8 Reserved RO - 7-0 RX Status Level. The value in this field sets the level, in number of DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be generated. When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. R/W 00h |
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