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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9220 датащи(PDF) 86 Page - Microchip Technology |
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LAN9220 датащи(HTML) 86 Page - Microchip Technology |
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86 / 142 page  LAN9220 DS00002417A-page 86 2006-2017 Microchip Technology Inc. 5.3.20 MAC_CSR_CMD – MAC CSR SYNCHRONIZER COMMAND REGISTER This register is used to control the read and write operations with the MAC CSR’s. 5.3.21 MAC_CSR_DATA – MAC CSR SYNCHRONIZER DATA REGISTER This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s. Offset: A4h Size: 32 bits Bits Description Type Default 31 CSR Busy. When a 1 is written into this bit, the read or write operation is performed to the specified MAC CSR. This bit will remain set until the operation is complete. In the case of a read this means that the host can read valid data from the data register. The MAC_CSR_CMD and MAC_CSR_DATA registers should not be modified until this bit is cleared. SC 0 30 R/nW. When set, this bit indicates that the host is requesting a read operation. When clear, the host is performing a write. R/W 0 29-8 Reserved. RO - 7-0 CSR Address. The 8-bit value in this field selects which MAC CSR will be accessed with the read or write operation. R/W 00h Offset: A8h Size: 32 bits Bits Description Type Default 31-0 MAC CSR Data. Value read from or written to the MAC CSR’s. R/W 00000000h |
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