LAN9220 datasheet(35/142 Pages) MICROCHIP

35 / 142 page

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DS00002417A-page 35

LAN9220

Table 3-9, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for each EEPROM

operation.

3.9.2.2

MAC Address Reload

The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register. If a value of 0xA5h

is not found in the first address of the EEPROM, the EEPROM is assumed to be un-programmed and MAC Address

Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. The EPC_-

LOAD bit is set after a successful reload of the MAC address.

3.9.2.3

EEPROM Command and Data Registers

Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 89 and Section 5.3.24, "E2P_DATA –

EEPROM Data Register," on page 91 for a detailed description of these registers. Supported EEPROM operations are

described in these sections.

3.9.2.4

EEPROM Timing

Refer to Section 6.11, "EEPROM Timing," on page 125 for detailed EEPROM timing specifications.

3.10

Power Management

The LAN9220 supports power-down modes to allow applications to minimize power consumption. The following sec-

tions describe these modes.

3.10.1

SYSTEM DESCRIPTION

Power is reduced to various modules by disabling the clocks as outlined in Table 3-10, “Power Management States,” on

page 37. All configuration data is saved when in either of the two low power states. Register contents are not affected

unless specifically indicated in the register description.

3.10.2

FUNCTIONAL DESCRIPTION

There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into

either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the

power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are for-

bidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also forbidden

until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest of the device be

accessed.

Note 3-4

The LAN9220 must always be read at least once after power-up, reset, or upon return from a power-

saving state, otherwise write operations will not function.

In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_C-

TRL register can be read to determine which LAN9220 device is driving the PME signal.

TABLE 3-9:

REQUIRED EECLK CYCLES

Operation

Required EECLK Cycles

ERASE

ERAL

EWDS

EWEN

READ

WRITE

WRAL

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