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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9220 датащи(PDF) 85 Page - Microchip Technology |
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LAN9220 датащи(HTML) 85 Page - Microchip Technology |
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85 / 142 page  2006-2017 Microchip Technology Inc. DS00002417A-page 85 LAN9220 5.3.18 FREE_RUN—FREE-RUN 25MHZ COUNTER This register reflects the value of the free-running 25MHz counter. 5.3.19 RX_DROP– RECEIVER DROPPED FRAMES COUNTER This register indicates the number of receive frames that have been dropped. Offset: 9Ch Size: 32 bits Bits Description Type Default 31:0 Free Running SCLK Counter (FR_CNT): Note: This field reflects the value of a free-running 32-bit counter. At reset the counter starts at zero and is incremented for every 25MHz cycle. When the maximum count has been reached the counter will rollover. Since the bus interface is 16-bits wide, and this is a 32-bit counter, the count value is latched on the first read. The FREE_RUN counter can take up to 160nS to clear after a reset event. Note: This counter will run regardless of the power management states D0, D1 or D2. RO - Offset: A0h Size: 32 bits Bits Description Type Default 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). RC 00000000h |
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