LAN9220 datasheet(76/142 Pages) MICROCHIP

76 / 142 page

LAN9220

DS00002417A-page 76

 2006-2017 Microchip Technology Inc.

5.3.9

HW_CFG—HARDWARE CONFIGURATION REGISTER

Offset:

74h

Size:

32 bits

Note:

The transmitter and receiver must be stopped before writing to this register. Refer to Section 3.12.8, "Stop-

ping and Starting the Transmitter," on page 51 and Section 3.13.4, "Stopping and Starting the Receiver,"

on page 56 for details on stopping the transmitter and receiver.

Bits

Description

Type

Default

Reserved

FIFO Port Endian Ordering (FPORTEND). This control bit determines the

endianess of RX and TX data FIFO host accesses when accessed through

the RX/TX Data FIFO ports, including the alias addresses (any access from

00h to 3Ch). When this bit is cleared, data FIFO port accesses utilize little

endian byte ordering. When this bit is set, data FIFO port accesses utilize

big endian byte ordering. Please refer to section Section 3.7.3, "Mixed

Endian Support," on page 26 for more information on this feature.

R/W

NASR

Direct FIFO Access Endian Ordering (FSELEND). This control bit

determines the endianess of RX and TX data FIFO host accesses when

accessed using the FIFO_SEL signal. When this bit is cleared, FIFO_SEL

accesses utilize little endian byte ordering. When this bit is set, FIFO_SEL

accesses utilize big endian byte ordering. Please refer to section Section

3.7.3, "Mixed Endian Support," on page 26 for more information on this

feature.

R/W

NASR

27-25

Reserved

AMDIX_EN Strap State. This read-only bit reflects the state of the

AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers

27.15 and 27.13

AMDIX

Strap

23-21

Reserved

Must Be One (MBO). This bit must be set to “1” for normal device

operation.

R/W

16-19

TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values

to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the

space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the

remaining space specified by TX_FIF_SZ. The minimum size of the TX

FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for

both TX data and TX commands.

The RX Status and data FIFOs consume the remaining space, which is

equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for

Configurable FIFO Memory Allocation," on page 77 for more information.

R/W

15-2

Reserved

Soft Reset Timeout (SRST_TO). If a software reset is attempted when the

PHY is not in the operational state (RX_CLK and TX_CLK running), the

reset will not complete and the soft reset operation will timeout and this bit

will be set to a ‘1’. The host processor must correct the problem and issue

another soft reset.

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