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LAN9220 датащи(PDF) 82 Page - Microchip Technology

номер детали LAN9220
подробное описание детали  16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
PDF  142 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9220 датащи(HTML) 82 Page - Microchip Technology

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LAN9220
DS00002417A-page 82
 2006-2017 Microchip Technology Inc.
5.3.14
GPIO_CFG—GENERAL PURPOSE IO CONFIGURATION REGISTER
This register configures the GPIO and LED functions.
Offset:
88h
Size:
32 bits
Bits
Description
Type
Default
31
Reserved
RO
-
30:28
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED
output. When cleared low, the pin functions as a GPIO signal.
LED1/GPIO0 – bit 28
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
R/W
000
27
Reserved
RO
-
26:24
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO
pin will set the corresponding INT_STS register bit.
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
Note:
GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
R/W
000
23
Reserved
RO
-
22:20
EEPROM Enable (EEPR_EN). The value of this field determines the
function of the external EEDIO and EECLK:
Please refer to Table 5-4 for the EEPROM Enable bit function definitions.
Note:
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not
use reserved settings.
R/W
000
19
Reserved
RO
-
18:16
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
corresponding GPIO signal is configured as a push/pull driver. When
cleared, the corresponding GPIO set configured as an open-drain driver.
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
R/W
000
15:11
Reserved
RO
-
10:8
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO
as output. When cleared the GPIO is enabled as an input.
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
R/W
0000
7:5
Reserved
RO
-



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