LAN9220 datasheet(56/142 Pages) MICROCHIP

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LAN9220

DS00002417A-page 56

 2006-2017 Microchip Technology Inc.

3.13.4

STOPPING AND STARTING THE RECEIVER

To stop the receiver, the host must clear the RXEN bit in the MAC Control Register. When the receiver is halted, the

RXSTOP_INT will be pulsed. Once stopped, the host can optionally clear the RX status and RX data FIFOs. The host

must re-enable the receiver by setting the RXEN bit.

3.13.5

RECEIVER ERRORS

If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be

asserted under the following conditions:

• A host underrun of RX data FIFO

• A host underrun of the RX status FIFO

• An overrun of the RX status FIFO

It is the duty of the host to identify and resolve any error conditions.

Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet

specification of 1518 bytes. This is only a frame too long indication and will not cause the frame

reception to be truncated.

Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision

window. This indicates that a late collision has occurred.

Frame Type. When set, this bit indicates that the frame is an Ethernet-type frame (Length/Type field

in the frame is greater than 1500). When reset, it indicates the incoming frame was an 802.3 type

frame. This bit is not set for Runt frames less than 14 bytes.

Receive Watchdog time-out. When set, this bit indicates that the incoming frame is greater than

2048 bytes through 2560 bytes, therefore expiring the Receive Watchdog Timer.

MII Error. When set, this bit indicates that a receive error (RX_ER asserted) was detected during

frame reception.

Dribbling Bit. When set, this bit indicates that the frame contained a non-integer multiple of 8 bits.

This error is reported only if the number of dribbling bits in the last byte is 4 in the MII operating mode,

or at least 3 in the 10 Mbps operating mode. This bit will not be set when the collision seen bit[6] is

set. If set and the CRC error bit[1] is cleared, then the packet is considered to be valid.

CRC Error. When set, this bit indicates that a CRC error was detected. This bit is also set when the

RX_ER pin is asserted during the reception of a frame even though the CRC may be correct. This bit

is not valid if the received frame is a Runt frame, or a late collision was detected or when the

Watchdog Time-out occurs.

Reserved. These bits are reserved. Reads 0

Bits

Description

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