LAN9220 datasheet(71/142 Pages) MICROCHIP

71 / 142 page

 2006-2017 Microchip Technology Inc.

DS00002417A-page 71

LAN9220

Power Management Event Interrupt (PME_INT). This interrupt is issued

when a Power Management Event is detected as configured in the

PMT_CTRL register. This interrupt functions independent of the PME

signal, and will still function if the PME signal is disabled. Writing a '1'

clears this bit regardless of the state of the PME hardware signal.

Note:

• Detection of a Power Management Event, and assertion of the PME

signal will not wakeup the LAN9220. The LAN9220 will only wake up

when it detects a host write cycle of any data to the BYTE_TEST reg-

ister.

• The Interrupt Deassertion interval does not apply to the PME interrupt.

R/WC

TX Status FIFO Overflow (TXSO). Generated when the TX Status

FIFO overflows.

R/WC

Receive Watchdog Time-out (RWT). Interrupt is generated when a

packet larger than 2048 bytes has been received.

R/WC

Receiver Error (RXE). Indicates that the receiver has encountered an

error. Please refer to Section 3.13.5, "Receiver Errors," on page 56 for a

description of the conditions that will cause an RXE.

R/WC

Transmitter Error (TXE). When generated, indicates that the

transmitter has encountered an error. Please refer to Section 3.12.7,

"Transmitter Errors," on page 51, for a description of the conditions that

will cause a TXE.

R/WC

12:11

Reserved

TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data

FIFO is full, and another write is attempted.

R/WC

TX Data FIFO Available Interrupt (TDFA). Generated when the TX data

FIFO available space is greater than the programmed level.

R/WC

TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status

FIFO is full.

R/WC

TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status

FIFO reaches the programmed level.

R/WC

RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued

whenever a receive frame is dropped.

R/WC

Reserved

RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status

FIFO is full.

R/WC

RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status

FIFO reaches the programmed level.

R/WC

2-0

GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s.

These interrupts are configured through the GPIO_CFG register.

R/WC

000

Bits

Description

Type

Default

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