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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9220 датащи(PDF) 103 Page - Microchip Technology |
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LAN9220 датащи(HTML) 103 Page - Microchip Technology |
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103 / 142 page  2006-2017 Microchip Technology Inc. DS00002417A-page 103 LAN9220 5.4.13 COE_CR—CHECKSUM OFFLOAD ENGINE CONTROL REGISTER This register controls the transmit and receive checksum offload engines. Offset: D Attribute: R/W Default Value: 00000000h Size: 32 bits Bits Description 31-17 Reserved 16 TX Checksum Offload Engine Enable (TXCOE_EN). This bit enables/disables the Transmit COE. This bit may only be changed if the TX data path is disabled. 0: The TXCOE is bypassed 1: The TXCOE is enabled 15-2 Reserved 1 RX Checksum Offload Engine Mode (RXCOE_MODE) This register indicates whether the RXCOE will check for VLAN tags or a SNAP header prior to beginning its checksum calculation. In its default mode, the calculation will always begin 14 bytes into the frame. The RXCOE_MODE may only be changed if the ESS RX path is disabled. 0: Begin checksum calculation after first 14 bytes of Ethernet Frame 1: Begin checksum calculation at start of L3 packet by adjusting for VLAN tags and/or SNAP header. 0 RX Checksum Offload Engine Enable (RXCOE_EN). This bit enables/disables the Receive COE. This bit may only be changed if the RX data path is disabled. 0: The RXCOE is bypassed 1: The RXCOE is enabled Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC_CR—MAC Control Register) and vice versa. These functions cannot be enabled simultaneously. |
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