PC97338VLJ datasheet(131/221 Pages) NSC

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4.3.10 EPP Data Port 3, Offset 7

This is the fourth EPP data port. It is only accessed to

transfer bits 24 to 31 of a 32-bit read or write to data

port 0.

FIGURE 71. EPP Data Port 3 Bitmap

4.3.11 EPP Mode Transfer Operations

The EPP transfer operations are: address read or

write, and data read or write. An EPP transfer opera-

tion is composed of a system read or write cycle (from

or to an EPP register) and an EPP read or write cycle

(from a peripheral device to an EPP register, or from

an EPP register to a peripheral device).

EPP 1.7 Address Write

The following procedure selects a peripheral device

or register as illustrated in Figure 72.

1. The system writes a byte to the EPP address reg-

ister.

WR becomes low to latch D7-0 into the address

PD7-0 and the EPP pulls WRITE low.

2. The EPP pulls ASTRB low to indicate that data

was sent.

3. If WAIT was low during the system write cycle, IO-

CHRDY becomes low. When WAIT becomes

high, the EPP pulls IOCHRDY high.

4. When IOCHRDY becomes high, it causes WR to

become high. If WAIT is high during the system

write cycle, then the EPP does not pull IOCHRDY

to low.

5. When WR becomes high, it causes the EPP to pull

ASTRB to high, and then to pull WRITE to high.

The EPP can change PD7-0 only when WRITE

and ASTRB are both high.

FIGURE 72. EPP 1.7 Address Write

EPP 1.7 Address Read

The following procedure reads from the address reg-

ister as shown in Figure 73.

1. The system reads a byte from the EPP address

2. The EPP pulls ASTRB low to signal the peripheral

to start sending data.

3. If WAIT is low during the system read cycle. Then

the EPP pulls IOCHRDY low. When WAIT be-

comes high, the EPP stops pulling IOCHRDY to

low.

4. When IOCHRDY becomes high, it causes RD to

become high. If WAIT is high during the system

read cycle then the EPP does not pull IOCHRDY

to low.

5. When RD becomes high, it causes the EPP to pull

ASTRB high. The EPP can change PD7-0 only

when ASTRB is high. After ASTRB becomes high,

the EPP puts D7-0 in TRI-STATE.

321

Reset

Required

EPP Data

Port 3

Offset 7

D26

D28

D29

D30

D31

D24

D25

D27

EPP Device

Read or Write

Bits 31-24

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

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