PC97338VLJ datasheet(128/221 Pages) NSC

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4.3.1

Enhanced Parallel Port (EPP)

Modes Register Set

Table 66 lists the EPP mode registers. All are single-

byte registers.

Bits 0, 1 and 3 of the CTR register must be 0 before

the EPP registers can be accessed, since the pins

controlled by these bits are controlled by hardware

during EPP accesses. Once these bits are set to 0 by

the software driver, multiple EPP access cycles may

be invoked. Bit 7 of the PTR register must be set to 0,

when EPP mode is enabled.

Bit 7 of STR (BUSY status) must be set to 1 before

writing to DTR in EPP mode to ensure data output to

PD7-0.

The EPP monitors the IOCHRDY pin during EPP cy-

cles. If IOCHRDY is driven low for more then 10

µsec,

an EPP time-out event occurs, which aborts the cycle

by asserting IOCHRDY, thus releasing the system

from a stuck EPP peripheral device. When the cycle

is aborted, ASTRB or DSTRB becomes inactive, and

the time-out event is signaled by asserting bit 0 of the

STR. If bit 4 of the CTR is 1, the time-out event also

pulses the IRQ5 or IRQ7 lines.

EPP cycles to the external device are activated by in-

voking read or write cycles to the EPP.

TABLE 66. Parallel Port Registers in EPP Modes

4.3.2

EPP Modes Parallel Port Register

Bitmaps

Offset

Symbol

Description

Mode

R/W

DTR

SPP Data

SPP or EPP R/W

STR

SPP Status SPP or EPP

CTR

SPP Control SPP or EPP R/W

EPP Address

EPP

R/W

EPP Data Port 0

EPP

R/W

EPP Data Port 1

EPP

R/W

EPP Data Port 2

EPP

R/W

EPP Data Port 3

EPP

R/W

654

Reset

Required

SPP or EPP Data

Offset 0

654

Reset

Required

SPP or EPP Status

Offset 1

IRQ Status

SLCT Status

PE Status

Time-Out Status

Reserved

ERR Status

654

Reset

Required

SPP or EPP Control

Offset 2

765

432

Reset

Required

EPP Address

Offset 3

EPP Device or

Printer Initialization Control(INIT)

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Automatic Line Feed Control

Parallel Port Input Control

ACK Status

Printer Status

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