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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC97338VLJ датащи(PDF) 129 Page - National Semiconductor (TI) |
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PC97338VLJ датащи(HTML) 129 Page - National Semiconductor (TI) |
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129 / 221 page  129 www.national.com 4.3.3 SPP or EPP Data Register (DTR), Offset 0 The DTR register is the SPP Compatible or SPP Ex- tended data register. A write to DTR sets the state of the eight data pins on the 25-pin D-shell connector. FIGURE 64. DTR Register Bitmap (EPP Mode) 4.3.4 SPP or EPP Status Register (STR), Offset 1 This status port is read only. A read presents the cur- rent status of the five pins on the 25-pin D-shell con- nector, and the IRQ as shown in Figure 65. FIGURE 65. STR Register Bitmap (EPP Mode) The bits of this register have the identical function in EPP mode as in SPP mode. See Section 4.2.4 for a detailed description of each bit. 4.3.5 SPP or EPP Control Register (CTR), Offset 2 This control port is read or write. A write operation to it sets the state of four pins on the 25-pin D-shell con- nector, and controls both the parallel port interrupt en- able and direction. 76 54 321 0 Reset Required 0 0 0 0 0 0 0 0 EPP Data Port 0 Offset 4 EPP Device Read or Write Bits 7-0 D2 D4 D5 D6 D7 D0 D1 D3 76 54 321 0 Reset Required 0 0 0 0 0 0 0 0 EPP Data Port 1 Offset 5 D10 D12 D13 D14 D15 D8 D9 D11 EPP Device Read or Write Bits 15-8 76 54 321 0 Reset Required 0 0 0 0 0 0 0 0 EPP Data Port 2 Offset 6 D18 D20 D21 D22 D23 D16 D17 D19 EPP Device Read or Write Bits 23-16 76 54 321 0 Reset Required 0 0 0 0 0 0 0 0 EPP Data Port 3 Offset 7 D26 D28 D29 D30 D31 D24 D25 D27 EPP Device Read or Write Bits 31-24 76 54 321 0 Reset Required 0 0 0 0 0 0 0 0 SPP or EPP Data Register (DTR) Offset 0 D2 D4 D5 D6 D7 D0 D1 D3 76 54 321 0 Reset Required 1 1 1 1 1 1 1 1 SPP or EPP Status Register (STR) Offset 1 IRQ Status SLCT Status PE Status Time-Out Status Reserved ERR Status ACK Status Printer Status |
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