PC97338VLJ datasheet(134/221 Pages) NSC

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TABLE 68. Parallel Port Registers in ECP Modes

4.4.1

Accessing the ECP Registers

The AFIFO, CFIFO, DFIFO and TFIFO registers ac-

cess the same ECP FIFO. The FIFO is accessed at

Base + 000h, or Base + 400h, depending on the mode

field of ECR and the register.

The FIFO can be accessed by system DMA cycles, as

well as system PIO cycles.

When the DMA is configured and enabled (bit 3 of

ECR is 1 and bit 2 of ECR is 0) the ECP automatically

(by hardware) issues DMA requests to fill the FIFO (in

the forward direction when bit 5 of DCR is 0) or to

empty the FIFO (in the reverse direction when bit 5 of

DCR is 1). All DMA transfers are to or from these reg-

isters. The ECP does not assert DMA requests for

more than 32 consecutive DMA cycles. The ECP

stops requesting the DMA when TC is detected during

an ECP DMA cycle.

Writing into a full FIFO, and reading from an empty

FIFO, are ignored. The written data is lost, and the

read data is undefined. The FIFO empty and full sta-

tus bits are not affected by such accesses.

Some registers are not accessible in all modes of op-

eration, or may be accessed in one direction only. Ac-

cessing a non accessible register has no effect. Data

read is undefined; data written is ignored; and the

FIFO does not update. The Chip SPP registers (DTR,

STR and CTR) are not accessible when the ECP is

enabled.

To improve noise immunity in ECP cycles, the state

machine does not examine the control handshake re-

sponse lines until the data has had time to switch.

In ECP modes:

• DATAR replaces DTR of SPP/EPP

• DSR replaces STR of SPP/EPP

• DCR replaces CTR of SPP/EPP

The base address is 278h, 378h or 3BCh, as speci-

fied in the FAR register in Legacy mode.

4.4.2

Software Operation in ECP Modes

Software should operate as described in “

Extended

Capabilities Port Protocol and ISA Interface Stan-

dard”.

Some of these operations are:

• Software should enable ECP (bit 2 of PCR is 1) af-

ter bits 3-0 of the parallel port Control Register

(CTR) are set to 0100.

• When ECP is enabled, software should switch

modes only through modes 000 or 001.

• When ECP is enabled, the software should

change direction only in mode 001.

• Software should not switch from mode 010 or 011,

to mode 000 or 001, unless the FIFO is empty.

• Software should switch to mode 011 when bits 0

and 1 of DCR are 0.

• Software should switch to mode 010 when bit 0 of

DCR is 0.

• Software should disable ECP (bit 2 of PCR is 0)

only in mode 000 or 001.

Software may switch from mode 011 backward to

modes 000 or 001, when there is an on-going ECP

read cycle. In this case, the read cycle is aborted by

deasserting AFD. The FIFO is reset (empty) and a po-

tential byte expansion (RLE) is automatically termi-

nated since the new mode is 000 or 001.

Offset Symbol

Description

Modes

(ECR Bits)

7 6 5

R/W

000h

DATAR

Parallel Port

Data Register

0 0 0

0 0 1

R/W

000h

AFIFO

ECP Address

FIFO

0 1 1

001h

DSR

Status Register

All Modes

002h

DCR

Control Register All Modes R/W

400h

CFIFO

Parallel Port

Data FIFO

0 1 0

400h

DFIFO

ECP Data FIFO

0 1 1

R/W

400h

TFIFO

Test FIFO

1 1 0

R/W

400h

CNFGA

Configuration

1 1 1

401h

CNFGB

Configuration

1 1 1

402h

ECR

Extended Control

All Modes R/W

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