PC97338VLJ datasheet(133/221 Pages) NSC

133 / 221 page

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FIGURE 75. EPP 1.9 Address Write

EPP 1.9 Address Read

The following procedure reads from the address reg-

ister.

1. The system reads a byte from the EPP address

IOCHRDY low, and waits for WAIT to become low.

2. When WAIT becomes low, the EPP pulls ASTRB

low and waits for WAIT to become high. If WAIT

was already low, steps 2 and 3 occur concurrently.

3. When WAIT becomes high, the EPP stops pulling

IOCHRDY low, and waits for RD to become high.

4. When RD becomes high, the EPP latches PD7-0

(to provide sufficient hold time), pulls ASTRB high,

and puts D7-0 in TRI-STATE.

FIGURE 76. EPP 1.9 Address Read

EPP 1.9 Data Write and Read

This procedure writes to the selected peripheral drive

or register.

EPP 1.9 data read and write operations are similar to

EPP 1.9 address read and write operations, respec-

tively, except that the data strobe (DSTRB signal) and

a data register replace the address strobe (ASTRB

signal) and the address register, respectively.

4.4

EXTENDED CAPABILITIES

PARALLEL PORT (ECP) MODES

In the Extended Capabilities Port (ECP) modes, the

device is a state machine that supports a 16-byte

FIFO that can be configured for either direction, com-

mand and data FIFO tags (one per byte), a FIFO

threshold interrupt for both directions, FIFO empty

and full status bits, automatic generation of strobes

(by hardware) to fill or empty the FIFO, transfer of

commands and data, and Run Length Encoding

(RLE) expanding (decompression) as explained be-

low. The FIFO can be accessed by PIO or system

DMA cycles.

The ECP modes are enabled when bit 2 of PCR is 1.

Once enabled, the mode is controlled via the mode

field of ECR, i.e., bits 7-5 of the ECR register as

shown in Table 71 on page 141 and described in de-

tail in “ECP Mode Descriptions” on page 142.

The ECP modes and their code designations are list-

ed in Table 67.

TABLE 67. ECP Modes Encoding

The output of the control signals in PC87338 are in

level 2 (pushpull) when:

- in ECP mode 011

- in ECP mode 010 and PCR[1]=1

The output of the control signals in PC97338 are in

level 2 (pushpull) in all ECP modes besides 000.

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

ECR Bit Encoding

Mode Name

Bit 7Bit 6Bit 5

Standard

001

PS/2

Parallel port FIFO

ECP FIFO

FIFO test

Configuration

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