PC97338VLJ datasheet(125/221 Pages) NSC

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The actual read or write to the data register is activat-

ed by the system RD and WR strobes.

Table 64 tabulates DTR register operation.

TABLE 64. SPP Data Register Read and Write

Modes

When bit 7 of the PTR is zero, the device is in SPP

compatible mode, and does not write data to the out-

put pins. Bit 5 of the CTR register has no effect in this

state. If data is written (WR goes low), the data will be

sent to the output pins PD7-0. If a Read cycle is initi-

ated (RD goes low), the system will read the contents

of the output latch, and not data from the output pins

PD7-0.

When bit 7 of the PTR is 1, the device is in the Extend-

ed SPP mode and can read and write external data

via PD7-0. In this mode, bit 5 sets the direction for

data in or data out, while read or write cycles are pos-

sible in both settings of bit 5.

If CTR bit 5 is cleared to 0, data is written to the output

pins PD7-0 when a write cycle occurs. (if a read cycle

occurs in this setting, the system will read the output

latch, not data from PD7-0).

If CTR bit 5 is set to 1, data is read from the output

pins PD7-0 when a read cycle occurs. A write cycle in

this setting will only write to the output latch, not to the

output pins PD7-0.

The reset value of this register is 0.

FIGURE 60. DTR Register Bitmap (SPP Mode)

4.2.4

Status Register (STR), Offset 1

This read-only register holds status information. A

system write operation to STR is an invalid operation

that has no effect on the parallel port.

FIGURE 61. STR Register Bitmap (SPP Mode)

Bit 0 - Time-Out Status

In EPP mode only, this is the time-out status bit. In

all other modes this bit has no function and has the

constant value 1.

This bit is cleared when EPP mode is enabled, i.e.,

when bit 0 of PCR is changed from 0 to 1. There-

after, this bit is set to 1 when a time-out occurs in

an EPP cycle and is cleared when STR is read.

In EPP mode:

0 - EPP mode set. No time-out occurred since

STR was last read.

1 - Time-out occurred on EPP cycle (minimum of

µsec). (Default)

Bit 1 - Reserved

This bit is reserved and is always 1.

Bit 7 of

PTR

Bit 5 of

CTR

RD WR

Result

Data written to PD7-0.

Data read from the

output latch

Data written to PD7-0.

Data written is latched

Data read from output

latch.

Data read from PD7-0.

321

Reset

Required

Data Register

(DTR)

Offset 0

321

Reset

Required

Status Register

(STR)

Offset 1

IRQ Status

SLCT Status

PE Status

ACK Status

Printer Status

Time-Out Status

Reserved

ERR Status

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