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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PC97307 датащи(PDF) 159 Page - National Semiconductor (TI) |
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PC97307 датащи(HTML) 159 Page - National Semiconductor (TI) |
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159 / 218 page  159 UART1 and UART2 (with IR) (Logical Devices 5 and 6) www.national.com 7.16 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS This Bank of registers controls aspects of the framing and timing of the infrared modes. TABLE 7-23. Bank 6 Register Set 7.16.1 Infrared Control Register 3 (IRCR3), Bank 6, Offset 00h This Register enables/disables modulation in Sharp-IR mode. Upon reset, the content of this register is 20h. FIGURE 7-33. IRCR3 Register Bitmap Bit 0-5 - Reserved Read/Write 0. Bit 6 - Sharp-IR Modulation Disable (SHMD_DS) 0 - Enables internal 500KHz transmitter modulation. (Default) 1 - Disables internal modulation. Bit 7 - Sharp-IR Demodulation Disable (SHDM_DS) 0 - Enables internal 500 KHz receiver demodulation. (Default) 1 - Disables internal demodulation. 7.16.2 Reserved Register, Bank 6, Offset 01h This register is reserved. Offset Register Name Description 00h IRCR3 Infrared Control Register 3 01h Reserved 02h SIR_PW SIR Pulse Width Control ( ≤ 115 Kbps) 03h LCR/ BSR Link Control Register/ Bank Select Register 04h - 07h Reserved 76543210 Reset Required 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Register 3 (IRCR3) Bank 6, Infrared Control SHMD_DS SHDM_DS Offset 00h Reserved 7.16.3 SIR Pulse Width Register (SIR_PW), Bank 6, Offset 02h This register sets the pulse width for transmitted pulses in SIR operation mode. These setting do not affect the receiv- er. Upon reset, the content of this register is 00h, which de- faults to a pulse width of 3/16 of the baud rate. FIGURE 7-34. SIR_PW Register Bitmap Bits 3-0 - SIR Pulse Width Register (SPW) Two codes for setting the pulse width are available. All other values for this field are reserved. 0000 - Pulse width is 3/16 of the bit period. (Default) 1101 - Pulse width is 1.6 µsec. Bits 7-4 - Reserved Read/Write 0’s. 7.16.4 Link Control Register (LCR) and Bank Select Register (BSR), Bank 6, Offset 03h These registers are the same as the registers at offset 03h in Bank 0. 7.16.5 Reserved Registers, Bank 6, Offsets 04h-07h These registers are reserved. 7.17 BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS Bank 7 contains the registers that configure Consumer-IR functions and infrared transceiver controls. See Table 7-24. TABLE 7-24. Bank 7 Register Set Offset Register Name Description 00h IRRXDC Infrared Receiver Demodulator Control Register 01h IRTXMC Infrared Transmitter Modulator Control Register 02h RCCFG Consumer-IR Configuration Reg- ister 03h LCR/BSR Link Control Register/ Bank Select Register 04h IRCFG1 Infrared Interface Configuration Register 1 76543210 Reset Required 0 0 0 0 0 0 0 0 0 0 0 0 Register (SIR_PW) Bank 6, SIR Pulse Width SPW(3-0) Offset 02h Reserved |
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