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PC97307 датащи(PDF) 157 Page - National Semiconductor (TI) |
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PC97307 датащи(HTML) 157 Page - National Semiconductor (TI) |
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157 / 218 page ![]() 157 UART1 and UART2 (with IR) (Logical Devices 5 and 6) www.national.com 7.13.2 Shadow of Link Control Register (SH_LCR), Bank 3, Offset 01h This register returns the value of the LCR register. The LCR register is written into when a byte value according to Table 7-9 on page 147, is written to the LCR/BSR registers loca- tion (at offset 03h) from any bank. FIGURE 7-29. SH_LCR Register Bitmap See “Link Control Register (LCR), All Banks, Offset 03h” on page 146 for bit descriptions. 7.13.3 Shadow of FIFO Control Register (SH_FCR), Bank 3, Offset 02h This read-only register returns the contents of the FCR reg- ister in bank 0. FIGURE 7-30. SH_LCR Register Bitmap See “FIFO Control Register (FCR), Bank 0, Offset 02h” on page 145 for bit descriptions. 7.13.4 Link Control Register (LCR) and Bank Select Register (BSR), Bank 3, Offset 03h These registers are the same as the registers at offset 03h in bank 0. 76543210 Reset Required 0 0 0 0 0 0 0 0 Link Control Register (SH_LCR) Bank 3, Shadow of STB EPS STKP SBRK BKSE WLS0 WLS1 PEN Offset 01h 76543210 Reset Required 0 0 0 0 0 0 0 0 FIFO Control Register (SH_FCR) Bank 3, Shadow of TXSR TXFTH0 TXFHT1 RXFTH0 RXFTH1 FIFO_EN RXSR Reserved Offset 02h 7.14 BANK 4 – IR MODE SETUP REGISTER TABLE 7-20. Bank 4 Register Set 7.14.1 Reserved Registers, Bank 4, Offsets 00h and 01h These registers are reserved. 7.14.2 Infrared Control Register 1 (IRCR1), Bank 4, Offset 02h Enables the Sharp-IR or SIR infrared mode in the Non-Ex- tended mode of operation. Upon reset, all bits are set to 0. FIGURE 7-31. IRCR1 Register Bitmap Bits 1,0 - Reserved Read/Write 0. Bits 3,2 - Sharp-IR or SIR Mode Select (IR_SL1,0), Non- Extended Mode Only These bits enable Sharp-IR and SIR modes in Non-Ex- tended mode. They allow selection of the appropriate in- frared interface when Extended mode is not selected. These bits are ignored when Extended mode is select- ed. Before running the legacy application in Sharp-IR or SIR Mode, run a small enabling routine to set bits 3 and 2 to the appropriate mode, i.e., 10 or 11 (see Table 7-21). The infrared application can then be executed and this module will be pre-set for the appropriate mode. Upon termination of the application these bits should be reset to 00 to switch back to a UART mode. Offset Register Name Description 00-01h Reserved 02h IRCR1 Infrared Control Register 1 03h LCR/ BSR Link Control/ Bank Select Registers 04-07h Reserved 76543210 Reset Required 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IRCR1) Bank 4, Infrared Control Register1 IR_SL0 Reserved Reserved IR_SL1 Offset 02h Reserved |
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