PC97307 datasheet(155/218 Pages) NSC

155 / 218 page

155

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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5. The modem status input pins (DSR, CTS, RI and DCD)

are disconnected. The internal modem status signals,

are driven by the lower bits of the MCR register.

Bit 5 - Enable Transmitter During Loopback (ETDLBK)

When this bit is set to 1, the transmitter serial output is en-

abled and functions normally when loopback is enabled.

Bit 6 - Reserved

Write 1.

Bit 7 - Baud Generator Test (BTEST)

When set, this bit routes the baud generator to the DTR

pin for testing purposes.

7.12.3

Link Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

7.12.4

Extended Control and Status Register 2

(EXCR2), Bank 2, Offset 04h

This register configures the transmitter and receiver FIFOs,

and the baud generator prescaler.

Upon reset all bits are set to 0.

FIGURE 7-25. EXCR2 Register Bitmap

Bits 1,0 - TX_FIFO Size (TF_SIZ1,0)

These bits select the number of levels for the TX_FIFO.

They are effective only when the FIFOs are enabled.

(See Table 7-16).

TABLE 7-16. TX_FIFO Size Encoding

Bits 3,2 - RX_FIFO Size (RF_SIZ1,0)

These bits select the number of levels for the RX_FIFO.

They are effective only when the FIFOs are enabled.

(See Table 7-17).

TF_SIZ1

TF_SIZ0

FIFO Depth

Reserved

76543210

Reset

Required

and Status Register 2

(EXCR2)

Bank 2,

Extended Control and

RF_SIZ0

PRESL0

PRESL1

Reserved

LOCK

TF_SIZ0

TF_SIZ1

RF_SIZ1

Offset 04h

TABLE 7-17. RX_FIFO Size Encoding

Bits 5,4 - Prescaler Select

The prescaler divides the 24 MHz input clock frequency

to provide the clock for the baud generator. (See Table

7-18).

TABLE 7-18. Prescaler Select

Bit 6 - Reserved

Read/write 0.

Bit 7 - Baud Divisor Register Lock (LOCK)

When set to 1, accesses to the baud generator divisor

back are disabled from non-extended mode.

In this case two scratchpad registers overlaid with LB-

GD(L) and LBGD(H) are enabled, and any attempted

CPU access of the baud generator divisor register

through LBGD(L) and LBGD(H) will access the scratch-

pad registers instead. This bit must be set to 0 when ex-

tended mode is selected.

7.12.5

Reserved Register, Bank 2, Offset 05h

This register is reserved.

Bits 7-0 - Reserved

Read/write 0’s.

7.12.6

TX_FIFO Current Level Register (TXFLV),

Bank 2, Offset 06h

This read-only register returns the number of bytes in the

TX_FIFO. It can be used to facilitate programmed I/O

modes during recovery from transmitter underrun in one of

the fast infrared modes.

RF_SIZ1

RF_SIZ0

FIFO Depth

reserved

Bit 5

Bit 4

Prescaler Value

1.625

Reserved

1.0

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