PC97307 datasheet(163/218 Pages) NSC

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163

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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7.17.3

Consumer-IR Configuration Register (RCCFG),

Bank 7, Offset 02h

This register control the basic operation of the Consumer-

IR mode. After reset, the content of this register is 00h.

FIGURE 7-37. RCCFG Register Bitmap

Bits 1,0 - Transmitter Modulator Mode (RC_MMD(1,0))

Determines how infrared pulses are generated from the

transmitted bit string. (see Table 7-30).

TABLE 7-30. Transmitter Modulation Mode Selection

Bit 2 - Transmitter Subcarrier Frequency Select

(TXHSC)

This bit selects the frequency range for the modulation

carrier.

0 - Low frequency: 30-56.9 KHz

1 - High frequency: 400-480 KHz

Bit 3 - Reserved

Read/Write 0.

Bit 4 - Receiver Demodulation Disable (RCDM_DS)

When this bit is 1, the internal demodulator is disabled.

The internal demodulator, when enabled, performs car-

rier frequency checking and envelope detection.

This bit must be set to 1 (disabled), when the demodu-

lation is performed externally, or when oversampling

mode is selected to determine the carrier frequency.

RCCFG

Bits

1 0

Modulation Mode

0 0

C_PLS Modulation mode. Pulses are

generated continuously for the entire logic

0 bit time.

0 1

8_PLS Modulation Mode. 8 pulses are

generated each time one or more logic 0

bits are transmitted following a logic 1 bit.

1 0

6_PLS Modulation Mode. 6 pulses are

generated each time one or more logic 0

bits are transmitted following a logic 1 bit.

1 1

Reserved. Result is indeterminate.

76543210

Reset

Required

Configuration Register

(RCCFG)

Bank 7,

Consumer-IR

RCDM_DS

Reserved

RXHSC

T_OV

R_LEN

RC_MMD0

RC_MMD1

TXHSC

Offset 02h

0 - Internal demodulation enabled.

1 - Internal demodulation disabled.

Bit 5 - Receiver Carrier Frequency Select (RXHSC)

This bit selects the frequency range for the receiver de-

modulator.

0 - Low frequency: 30-56.9 KHz

1 - High frequency: 400-480 KHz

Bit 6 - Receiver Sampling Mode Select(T_OV)

0 - Programmed-T-period sampling.

1 - Oversampling mode.

Bit 7 - Run Length Control (R_LEN)

Enables or disables run length encoding/decoding. The

format of a run length code is:

YXXXXXXX

where, Y is the bit value and XXXXXXX is the number

of bits minus 1 (Selects from 1 to 128 bits).

0 - Run Length Encoding/decoding is disabled.

1 - Run Length Encoding/decoding is enabled.

7.17.4

Link Control/Bank Select Registers (LCR/BSR),

Bank 7, Offset 03h

These registers are the same as the registers at offset

03h in bank 0.

7.17.5

Infrared Interface Configuration Register 1

(IRCFG1), Bank 7, Offset 04h

This register holds the transceiver configuration data for

Sharp-IR and SIR modes. It is also used to directly control

the transceiver operation mode when automatic configura-

tion is not enabled. The four least significant bits are also

used to read the identification data of a Plug and Play infra-

red interface adaptor.

FIGURE 7-38. IRCFG1 Register Bitmap

Bit 0 - Transceiver Identiﬁcation/Control Bit 0 (IRIC0)

The function of this bit depends on whether the

ID0/IRSL0/IRRX2 pin is programmed as an input or an

output.

If ID0/IRSL0/IRRX2 is programmed as an input

(IRSL0_DS = 0) then:

— Upon read, this bit returns the logic level of the pin

(allowing external devices to identify themselves).

— Data written to this bit position is ignored.

76543210

Reset

Required

Infrared Configuration

(IRCFG1)

Bank 7,

IRIC(2-0)

SIRC(2-0)

IRID3

STRV_MS

Offset 04h

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