PC97307 datasheet(158/218 Pages) NSC

158 / 218 page

158

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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TABLE 7-21. Sharp-IR or SIR Mode Selection

Bits 7-4 - Reserved

Read/Write 0.

7.14.3

Link Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

7.14.4

Reserved Registers, Bank 4, Offsets 04h -07h

These registers are reserved.

7.15 BANK 5 – INFRARED CONTROL REGISTERS

TABLE 7-22. Bank 5 Registers

7.15.1

Reserved Registers, Bank 5, Offsets 00h -02h

These registers are reserved.

7.15.2

(LCR/BSR) Register, Bank 5, Offset 03h

These registers are the same as the registers at offset 03h

in bank 0.

7.15.3

Infrared Control Register 2 (IRCR2), Bank 5,

Offset 04h

This register controls the basic settings of the infrared modes.

Upon reset, the content of this register is 02h.

IR_SL1

IR_SL0

Selected Mode

UART (Default)

Reserved

Sharp-IR

SIR

Offset

Name

Description

00-02h

Reserved

03h

LCR/

BSR

Link Control Register/

Bank Select Register

04h

IRCR2

Infrared Control Register 2

05h - 07h

Reserved

FIGURE 7-32. IRCR2 Register Bitmap

Bit 0 - Enable Infrared Full Duplex Mode (IR_FDPLX)

When set to 1, the infrared receiver is not masked dur-

ing transmission.

Bit 1 - MSR Register Function Select in Infrared Mode

(IRMSSL)

This bit selects the behavior of the Modem Status Reg-

ister (MSR) and the Modem Status Interrupt (MS_EV)

when any infrared mode is selected. When a UART

mode is selected, the Modem Status Register and the

Modem Status Interrupt function normally, and this bit is

ignored.

0 - MSR register and modem status interrupt work in

the IR modes as in the UART mode (Enables ex-

ternal circuitry to perform carrier detection and pro-

vide wake-up events).

1 - The MSR returns 30h, and the Modem Status Inter-

rupt is disabled. (Default)

Bits 3,2 -Reserved

Read/Write 0.

Bit 4 - Auxiliary Infrared Input Select (AUX_IRRX)

When set to 1, the infrared signal is received from the

auxiliary input. (Separate input signals may be desired

for different front-end circuits). See Table 7-31 on page

165.

Bit 5-7 - Reserved

Read/Write 0.

7.15.4

Reserved Registers, Bank 5, Offsets 05h -07h

These registers are reserved.

76543210

Reset

Required

(IRCR2)

Bank 5,

AUX_IRRX

IR_FDPLX

IRMSSL

Infrared Control

Offset 04h

Reserved

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