PC97307 datasheet(154/218 Pages) NSC

154 / 218 page

154

UART1 and UART2 (with IR) (Logical Devices 5 and 6)

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7.12.2

Extended Control Register 1 (EXCR1),

Bank 2, Offset 02h

Use this register to control module operation in the Extend-

ed mode. Upon reset all bits are set to 0.

FIGURE 7-23. EXCR1 Register Bitmap

Bit 0 - Extended Mode Select (EXT_SL)

When set to 1, the Extended mode is selected.

Bit 1 - DMA Fairness Control (DMANF)

This bit controls the maximum duration of DMA burst

transfers.

0 - DMA requests are forced inactive after approxi-

mately 10.5

µsec of continuous transmitter and/or

receiver DMA operation. (Default)

1 - A transmission DMA request is deactivated when

the TX_FIFO is full. A reception DMA request is de-

activated when the RX_FIFO is empty.

Bit 2 - DMA FIFO Threshold (DMATH)

This bit selects the TX_FIFO and RX_FIFO threshold

levels used by the DMA request logic to support de-

mand transfer mode.

A transmission DMA request is generated when the

TX_FIFO level is below the threshold.

A reception DMA request is generated when the

RX_FIFO level reaches the threshold or when a DMA

timeout occurs.

Table 7-15 lists the threshold levels for each FIFO.

TABLE 7-15. DMA Threshold Levels

Bit 3 - DMA Swap (DMASWP)

This bit selects the routing of the DMA control signals

between the internal DMA logic and the configuration

module of the chip. When this bit is 0, the transmitter

Bit

Value

DMA Threshold for FIFO Type

RX_FIFO

Tx_FIFO

(16 Levels)

Tx_FIFO

(32 Levels)

110

76543210

Reset

Required

and Status Register 1

(EXCR1)

Bank 2,

Extended Control and

DMATH

LOOP

ETDLBK

Reserved

BTEST

EXT_SL

DMANF

DMASWP

Offset 02h

and receiver DMA control signals are not swapped.

When it is 1, they are swapped. A block diagram illus-

trating the control signals routing is given in Fig. 7-24.

The swap feature is particularly useful when only one

8237 DMA channel is used to serve both transmitter and

receiver. In this case only one external DRQ/DACK sig-

nal pair will be interconnected to the swap logic by the

configuration module. Routing the external DMA chan-

nel to either the transmitter or the receiver DMA logic is

then simply controlled by the DMASWP bit. This way,

the infrared device drivers do not need to know the de-

tails of the configuration module.

FIGURE 7-24. DMA Control Signals Routing

Bit 4 - Loopback Enable (LOOP)

During loopback, the transmitter output is connected in-

ternally to the receiver input, to enable system self-test

of serial communications. In addition to the data signal,

all additional signals within the UART are interconnect-

ed to enable real transmission and reception using the

UART mechanisms.

When this bit is set to 1, loopback is selected. This bit

accesses the same internal register as bit 4 in the MCR

Loopback behaves similarly in both Non-Extended and

Extended modes.

When Extended mode is selected, the DTR bit in the

MCR register internally drives both DSR and RI, and the

RTS bit drives CTS and DCD.

During loopback, the following actions occur:

1. The transmitter and receiver interrupts are fully op-

erational. The Modem Status Interrupts are also fully

operational, but the interrupt sources are now the

lower bits of the MCR register. Modem interrupts in

infrared modes are disabled unless the IRMSSL bit

in the IRCR2 register is 0. Individual interrupts are

still controlled by the IER register bits.

2. The DMA control signals are fully operational.

3. UART and infrared receiver serial input signals are

disconnected. The internal receiver input signals are

connected to the corresponding internal transmitter

output signals.

4. The UART transmitter serial output is forced high

and the infrared transmitter serial output is forced

low, unless the ETDLBK bit is set to 1. In which case

they function normally.

TX -

Routing

RX_DMA

Logic

Channel

DMA

Logic

TX -

Channel

DMA

Logic

TX_DMA

DMA

Hand-

shake

Signals

DMASWP

DMA Swap

Logic

Conﬁguration

Module

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