PC87413 datasheet(176/257 Pages) NSC

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9.0 System Wake-Up Control (SWC) (Continued)

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Revision1.2

9.3

SWC REGISTERS

The SWC registers are organized in four banks. The offsets are related to the base address determined by the SWC Base

Address register at indexes 60h - 61h in the SWC device configuration. The lower 16 offsets (00h-0Fh) are common to the

four banks; the upper offsets (10h-1Fh) are divided as follows:

• Bank 0 holds registers related to the Keyboard/Mouse Wake-up Detector.

• Bank 1 holds registers related to the Power Active timers.

• Bank 2 holds registers related to sleep states and ACPI configuration.

• Bank 3 holds registers related to the watchdog.

The active bank is selected through the BNK_SEL1-BNK_SEL0 bits in the Bank Select register (BANKSEL). For details, see

Section 9.3.15 on page 192.

The following abbreviations are used to indicate the Register Type:

R/W

= Read/Write.

= Read from a speciﬁc register (write to the same address is to a different register).

= Write (see above).

= Read Only.

= Write Only. Reading from the bit returns 0.

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.

9.3.1

SWC Register Map

The following tables list the SWC registers. For the SWC register bitmap, see Section 9.5 on page 216. Most of the registers

are battery backed, however some are VSB powered.

Table 43. Banks 0, 1, 2 and 3 - Common Register Map

Offset

Mnemonic

Type

Power Well Section

00h

WK_EVT_SEL

Wake-Up Event Select

R/W

VPP

9.3.2

01h

WK_ST_EN

Wake-Up State Enable

R/W

VPP

9.3.3

02h

GPE1_2IRQ_LOW

GPE1_STS Events to IRQ Enable Low

R/W

VPP

9.3.4

03h

GPE1_2IRQ_HIGH

GPE1_STS Events to IRQ Enable High

R/W

VPP

9.3.5

04h

GPE1_2SMI_LOW

GPE1_STS Events to SMI Enable Low

R/W

VPP

9.3.6

05h

GPE1_2SMI_HIGH

GPE1_STS Events to SMI Enable High

R/W

VPP

9.3.7

06h

SWCFDIS

SWC Fast Disable

R/W

VSB

9.3.8

07h

SWCTRIS

SWC TRI-STATE

R/W

VSB

9.3.9

08h

SWC_CTL

SWC Miscellaneous Control

Varies per bit

VPP

9.3.10

09h

PWONCTL

Power On Control

Varies per bit

VPP

9.3.11

0Ah

LEDCTL

LED Control

R/W

VPP

9.3.12

0Bh

LEDBLNK

LED Blinking Control

R/W

VPP

9.3.13

0Ch-0Dh Reserved

0Eh

BIOSGPR

BIOS General-Purpose Scratch

R/W

VPP

9.3.14

0Fh

BANKSEL

Bank Select

R/W

VPP

9.3.15

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