PC87413 datasheet(174/257 Pages) NSC

174 / 257 page

9.0 System Wake-Up Control (SWC) (Continued)

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Revision1.2

• 00b − The behavior of the LED1 and LED2 pins is controlled by software only (through the setting of the LED1BLNK and

LED2BLNK fields), except for the Power Fail state (VSB and VDD off) when both LEDs are Off.

• 01b − The behavior of the LED1 and LED2 pins is controlled by the power states and by software.

In the Power Fail state (VSB and VDD off), both LEDs are Off;

In the Power Off state (VSB on and VDD off), both LEDs blink at a 1 Hz rate, with a 50% duty cycle;

In the Power On state (VSB and VDD on), each LED behaves according to the setting of its LEDxBLNK field.

• 10b − The behavior of the LED1 and LED2 pins is controlled by the S3I sleep state and by software.

In the Power Fail state (VSB and VDD off) and in the S45 sleep state, both LEDs are Off;

In the Power On state (VSB and VDD on) and in the S3I sleep state, each LED behaves according to the setting of its

LEDxBLNK field.

• 11b − The behavior of the LED1 and LED2 pins is controlled by the sleep states and by software.

In the Power Fail state (VSB and VDD off), both LEDs are Off;

In the Power On state (VSB and VDD on) and in the S45 and S3I sleep states, each LED behaves according to the setting

of its LEDxBLNK field.

9.2.8

Power Active Timers

The SWC includes two 32-bit Power Active timers: a VDD Active Timer, and a VSB Active Timer. Each timer is clocked by a

1 Hz internal clock derived from the battery-backed 32.768 kHz crystal clock generator.

These timers measure the cumulative amount of time (in seconds) that the VSB and the VDD power supplies are active (On).

Each of them is enabled for counting when its related power supply is turned on and stops counting when the power supply

goes off.

Due to their 32-bit length, the timers do not need to be reset; however, a reset bit is available for each timer (VSB_TMR_RST

and VDD_TMR_RST) in the PWTMRCTL register (see Section 9.3.29 on page 199).

The timer count data of the VDD Active Timer is available to the software in the VDD_ON_TMR_0 to VDD_ON_TMR_3 read-

only registers (see Sections 9.3.21 to 9.3.24 on pages 196ff.), which are updated each second with the actual count value

of the timer. When VDD_ON_TMR_0 (the LSByte of the count data) is read, the updating of all four registers

(VDD_ON_TMR_0

VDD_ON_TMR_3)

stopped,

freezing

the

count

value.

The

VDD_ON_TMR_1

and

VDD_ON_TMR_2 registers can then be read in any order. Finally, reading from the VDD_ON_TMR_3 register resumes the

registers updating with the actual count value of the timer. Therefore, the VDD_ON_TMR_0 register must be read first and

the VDD_ON_TMR_3 register last.

The same applies for the VSB Active Timer, whose timer count data is available to the software in the VSB_ON_TMR_0 to

VSB_ON_TMR_3 read-only registers (see Sections 9.3.25 to 9.3.28 on pages 197ff.).

9.2.9

Watchdog Function

The watchdog includes an 8-bit timer clocked by a 1-minute internal clock that is derived from the battery-backed 32.768

KHz crystal clock generator. The timer is loaded with the Watchdog Time-Out Data value written in the WDTO register (see

Section 9.3.34 on page 202) and counts down to zero. This 8-bit data enables time-out values between 1 to 255 minutes to

be programmed (00h is an invalid data value).

Five events can trigger the watchdog by reloading the timer:

Keyboard interrupt.

Mouse interrupt.

Serial Port 1 interrupt.

Serial Port 2 interrupt.

Software writing a ‘1’ to the SW_WD_TRG bit of the WDCTL register (see Section 9.3.33 on page 202).

Each event can be masked by an enable bit in the WDCFG register (see Section 9.3.35 on page 203). Whenever an active

edge of any enabled event is detected, the timer is restarted from the Watchdog Time-Out Data value. If no event occurs

before the timer reaches 00h, the WDO_EVT_STS status bit in the GPE1_STS_3 register (see Section 9.4.11 on page 211)

is set to ‘1’ and a 250 ms active low pulse is generated at the WDO pin. After a watchdog time-out or when the Hardware

reset is active (LRESET), the timer is reloaded.

The WDO_EVT_STS status bit can be routed either to the SIOSMI pin by the WDO_EVT_2SMI bit in the GPE1_2SMI_HIGH

Section 9.4.15 on page 215).

After either VSB Power-up reset or VDD Power-up reset, the watchdog is disabled. Its operation is enabled by setting the

WDEN bit in the WDCTL register (see Section 9.3.33 on page 202) to ‘1’. Once set, this bit cannot be cleared by software.

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