PC87413 datasheet(171/257 Pages) NSC

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9.0 System Wake-Up Control (SWC) (Continued)

Revision 1.2

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In addition, a wake-up mechanism can be enabled to trigger a 100 ms pulse at the PWBTOUT output on each valid wake-

up event. This wake-up mechanism is routed to the PWBTOUT pulse generator only if the PWBTOUT_MODE bit in the

ACPI_CFG register (see Section 9.3.32 on page 201) is reset.

The PWBTOUT wake-up mechanism is similar to the one described for the ONCTL signal, as follows:

It is based on status bits in the GPE1_STS_0 to GPE1_STS_3 registers and in the PM1b_STS_HIGH register (ex-

cept the PWBT_EVT_STS and the PWRBTN_STS bits).

It is not affected by the Watchdog Status bit (WDO_EVT_STS).

It is independent of the enable bits in the GPE1_EN_0 to GPE1_EN_3 registers and in the PM1b_EN_HIGH register.

It is dependent only on the S3I and S45 current sleep states.

Its conﬁguration bits are also located in the WK_ST_EN register, which is accessed by writing the event index value

into the WKUPSEL field of the WK_EVT_SEL register.

The PWBT_EN_S3I and PWBT_EN_S45 bits control the generation of a wake-up pulse on PWBTOUT by an active event

(currently accessed through the WK_EVT_SEL register) when the PC8741x device is in S3I or in S45 current state, respec-

tively.

Any valid wake-up event is disabled from generating a wake-up pulse on PWBTOUT for 1 second after the power supply

has been turned off (by setting ONCTL = 1). If the Keyboard/Mouse Power Control feature (VDDFELL) is enabled by setting

the VDDFLMUX bit to ‘1’ (in the SIOCF2 register; see Section 3.7.3 on page 50), the Keyboard and Mouse wake-up events

are disabled from generating a wake-up pulse for 2 seconds after the power supply has been turned off (by setting ONCTL

= 1).

A PWBTOUT pulse is generated only when the VDD power is not present or when a PWBTIN pulse occurred.

Figure 51. PWBTOUT Control

GPE1_STS_0-3

Status

Set

PWBTOUT

State S3I

From Other

Enabled Events

State S45

PWBT_

EN_S45

PWBT_

EN_S3I

Off

Crowbar

1 Second

Pulse

Detected

Event

(one of 30

100 ms

Pulse

No_Vdd

PWBTIN

PWBTOUT

_MODE

Resume

from

Power Fail

4 s

Pulse

Status

Set

PWBTIN

events;

PWBTN is

separate)

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