PC87413 datasheet(148/257 Pages) NSC

148 / 257 page

8.0 Real-Time Clock (RTC) (Continued)

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148

Revision1.2

If the RTC oscillator becomes inactive, the following features are dysfunctional/disabled:

Timekeeping.

Periodic interrupt.

Alarm.

8.2.13

Interrupt Handling

The RTC has a single Interrupt Request line which handles the following three interrupt conditions:

Periodic interrupt.

Alarm interrupt.

Update end interrupt.

The interrupts are generated if the respective enable bits in the CRB register are set prior to an interrupt event occurrence.

Reading the CRC register clears all interrupt flags. Thus, when multiple interrupts are enabled, the interrupt service routine

must first read and store the CRC register and then deal with all pending interrupts by referring to this stored status.

If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost.

Figure 46 illustrates the interrupt and status timing in the RTC.

Figure 46. Interrupt/Status Timing

8.2.14

Battery-Backed RAMs and Registers

The RTC has two battery-backed RAMs and 17 registers used by the logical units themselves. Battery-backup power en-

ables information retention during system power down.

The RAMs are:

Standard RAM.

Extended RAM.

The memory maps and register content of the RAMs are illustrated in Section 8.6 on page 160.

The first 14 bytes and three programmable bytes of the Standard RAM are overlaid by time, alarm data and control registers.

The remaining 111 bytes are general-purpose memory.

Registers with reserved bits must be written using the “Read-Modify-Write” method.

All register locations within the device are accessed by the RTC Index and Data registers (at base address and base ad-

dress+1). The Index register points to the register location being accessed. The Data register contains the data to be trans-

ferred to or from the location. An additional 128 bytes of battery-backed RAM (also called Extended RAM) may be accessed

via a second pair of Index and Data registers pointed at by the secondary base address and base address+1.

Access to the two RAMs may be locked. For details see the RAM Lock Register (RLR) in Section 3.16.3 on page 88.

Flags (and IRQ) are reset at the conclusion

of CRC read or by reset.

Update In Progress bit high before update occurs = 244

µs

Periodic interrupt to update = (P/2 + A)

Update to Alarm Interrupt = 30.5

µs

Periodic interrupt cycle (programmed by RS3-0 of CRA)

Bit 7 of CRA

Bit 4

Bit 6

Bit 5

of CRC

P/2

(244

µs)

(30.5

µs)

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