PC87413 datasheet(145/257 Pages) NSC

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8.0 Real-Time Clock (RTC) (Continued)

Revision 1.2

145

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8.2.7

Updating

The time and calendar registers are updated once per second regardless of bit 7 (SET) of the CRB register. Since the time

and calendar registers are updated serially, unpredictable results may occur if they are accessed during the update. There-

fore, it is essential to ensure that reading or writing to the time storage locations does not coincide with a system update of

these locations. There are four methods to avoid this contention.

Method 1

1. Set bit 7 of the CRB register to 1. This takes a “snapshot” of the internal time registers and loads them into the user copy

registers. The user copy registers are seen when accessing the RTC from outside and are part of the double buffering

mechanism. This bit may be kept set for up to 1 second, since the time/calendar chain continues to be updated once per

second.

2. Read or write the required registers (since bit 7 is set, the access is to the user copy registers). If a read operation is

performed, the information read is correct from the time bit 7 was set. If a write operation is performed, the write is only

to the user copy registers.

3. Reset bit 7 to 0. During the transition, the user copy registers update the internal registers, using the double buffering

mechanism to ensure that the update is performed between two time updates. This mechanism enables new time pa-

rameters to be loaded in the RTC.

Method 2

1. Access the RTC registers after detection of an Update Ended interrupt. The detection interrupt implies that an update

has just been completed and 999 ms remain until the next update.

2. To detect an Update Ended interrupt, either:

— Poll bit 4 of the CRC register.

— Use the following interrupt routine:

a) Set bit 4 of the CRB register.

b) Wait for an interrupt from interrupt pin.

c) Clear the IRQF flag of the CRC register before exiting the interrupt routine.

Method 3

Poll bit 7 of the CRA register. The update occurs 244

µs after this bit goes high. Therefore, if a 0 is read, the time registers

remain stable for at least 244

µs.

Method 4

Use a periodic interrupt routine to determine if an update cycle is in progress, as follows:

1. Set the periodic interrupt to the desired period.

2. Set bit 6 of the CRB register to enable the interrupt from periodic interrupt.

3. Wait for the appearance of a periodic interrupt, which indicates that the period represented by the following expression

remains until another update occurs:

[(Period of periodic interrupt

/ 2) + 244 µs]

8.2.8

Alarms

The timekeeping function can be set to generate an alarm when the current time reaches a stored alarm time. After each

RTC time update (every 1 second), the seconds, minutes, hours, date-of-month and month counters are compared with their

corresponding registers in the alarm settings. If they are equal, bit 5 of the CRC register is set to 1 and sent to the SWC as

an alarm signal. If the Alarm Interrupt Enable bit was previously set (bit 5 of the CRB register), the interrupt request pin is

also active.

Any alarm register may be set to Unconditional Match by setting bits 7 and 6 to binary ‘11’. This combination, not used by

any BCD or binary time codes, results in a periodic alarm. The rate of this periodic alarm is determined by the registers that

were set to Unconditional Match.

For example, if all but the seconds and minutes alarm registers are set to Unconditional Match, an interrupt is generated

every hour at the specified minute and second. If all but the seconds, minutes and hours alarm registers are set to Uncon-

ditional Match, an interrupt is generated every day at the specified hour, minute and second.

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