PC87413 datasheet(147/257 Pages) NSC

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8.0 Real-Time Clock (RTC) (Continued)

Revision 1.2

147

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Figure 44. Typical Battery Current During Battery-Backed Power Mode

Figure 45. Typical Battery Current During Normal Operation Mode

8.2.10

System Bus Lockout

During power On or power Off, spurious bus transactions from the host may occur. To protect the data in the RTC internal

registers from being corrupted, all inputs are automatically locked out. The lockout condition is asserted when VSB is lower

than VSBON at VSB power-on or VSBOFF at VSB power-off.

8.2.11

Power-Up Detection

When system power is restored after a power failure or power off state (VSB=0), the lockout condition continues for a delay

of 62 ms (minimum) to 125 ms (maximum) after the RTC switches from battery to system power.

The lockout condition is switched off immediately in the following situations:

• If the Divider Chain Control bits, DV0-2 (bits 6-4 in the CRA register), specify a normal operation mode (010), all input

signals are enabled immediately on detection of system voltage above VSBON.

• When battery voltage is below V

BATDCT and LRESET is 0, all input signals are enabled immediately on detection of sys-

tem voltage above VSBON. This also initializes registers at offsets 00h through 0Dh.

• If bit 7 (VRT) of the CRD register is 0, all input signals are enabled immediately on detection of system voltage above

VSBON.

8.2.12

Oscillator Activity

The RTC oscillator is active if:

VSB power supply is higher than VSBON regardless of the battery voltage, VBAT.

VBAT power supply is higher than VBATMIN whether or not VSB is present.

The RTC oscillator is disabled if:

During power-down (VBAT only), if the battery voltage drops below VBATMIN, Battery Fail state may be entered. In this

case, the oscillator may stop oscillating and memory contents may be corrupted or lost.

Software writes 00h to DV2-0 bits of the CRA register and VSB is removed. This disables the oscillator and decreases

the power consumption from the battery connected to the VBAT pin. When disabling the oscillator, the CMOS RAM is

not affected as long as the battery is present at a correct voltage level.

IBAT (µA)

1.0

0.9

0.8

0.7

2.4 3.0 3.6

VBAT (V)

IBAT (µA)

0.20

0.15

0.10

0.05

3.0 3.3 3.6

VSB

Note: Battery voltage in this test is 3.0V.

(V)

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