PIC17C752-08SLASHCL datasheet(107/328 Pages) MICROCHIP

107 / 328 page

DS30289A-page 107

PIC17C7XX

13.1.3.3

EXTERNAL CLOCK SOURCE

The PWMs will operate regardless of the clock source

of the timer. The use of an external clock has ramiﬁca-

tions that must be understood. Because the external

TCLK12 input is synchronized internally (sampled once

per instruction cycle), the time TCLK12 changes to the

time the timer increments will vary by as much as 1TCY

(one instruction cycle). This will cause jitter in the duty

cycle as well as the period of the PWM output.

This jitter will be

±1TCY, unless the external clock is

synchronized with the processor clock. Use of one of

the PWM outputs as the clock source to the TCLK12

input, will supply a synchronized clock.

In general, when using an external clock source for

PWM, its frequency should be much less than the

device frequency (Fosc).

13.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR

EXTERNAL CLOCK INPUT

The use of an external clock for the PWM time-base

(Timer1 or Timer2) limits the PWM output to a maxi-

mum resolution of 8-bits. The PWxDCL<7:6> bits must

be kept cleared. Use of any other value will distort the

PWM output. All resolutions are supported when inter-

nal clock mode is selected. The maximum attainable

frequency is also lower. This is a result of the timing

requirements of an external clock input for a timer (see

the Electrical Speciﬁcation section). The maximum

PWM frequency, when the timers clock source is the

RB4/TCLK12 pin, as shown in Table 13-4 (standard

resolution mode).

TABLE 13-5:

REGISTERS/BITS ASSOCIATED WITH PWM

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

MCLR,

WDT

16h, Bank 3

TCON1

CA2ED1

CA2ED0

CA1ED1

CA1ED0

T16

TMR3CS

TMR2CS

TMR1CS

0000 0000

17h, Bank 3

TCON2

CA2OVF

CA1OVF

PWM2ON

PWM1ON

CA1/PR3

TMR3ON

TMR2ON

TMR1ON

0000 0000

16h, Bank 7

TCON3

—

CA4OVF

CA3OVF

CA4ED1

CA4ED0

CA3ED1

CA3ED0

PWM3ON

-000 0000

10h, Bank 2

TMR1

Timer1’s register

xxxx xxxx

uuuu uuuu

11h, Bank 2

TMR2

Timer2’s register

xxxx xxxx

uuuu uuuu

16h, Bank 1

PIR1

RBIF

TMR3IF

TMR2IF

TMR1IF

CA2IF

CA1IF

TX1IF

RC1IF

x000 0010

u000 0010

17h, Bank 1

PIE1

RBIE

TMR3IE

TMR2IE

TMR1IE

CA2IE

CA1IE

TX1IE

RC1IE

0000 0000

07h, Unbanked

INTSTA

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

0000 0000

06h, Unbanked

CPUSTA

—

STKAV

GLINTD

POR

BOR

--11 11qq

--11 qquu

14h, Bank 2

PR1

Timer1 period register

xxxx xxxx

uuuu uuuu

15h, Bank 2

PR2

Timer2 period register

xxxx xxxx

uuuu uuuu

10h, Bank 3

PW1DCL

DC1

DC0

—

xx-- ----

uu-- ----

11h, Bank 3

PW2DCL

DC1

DC0

TM2PW2

—

xx0- ----

uu0- ----

10h, Bank 7

PW3DCL

DC1

DC0

TM2PW3

—

xx0- ----

uu0- ----

12h, Bank 3

PW1DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

13h, Bank 3

PW2DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

11h, Bank 7

PW3DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,

shaded cells are not used by PWM Module.

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