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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC17C752-08/CL датащи(PDF) 111 Page - Microchip Technology |
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PIC17C752-08/CL датащи(HTML) 111 Page - Microchip Technology |
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111 / 328 page  © 1998 Microchip Technology Inc. DS30289A-page 111 PIC17C7XX 13.2.3 READING THE CAPTURE REGISTERS The Capture overflow status flag bits are double buffered. The master bit is set if one captured word is already residing in the Capture register and another “event” has occurred on the CAPx pin. The new event will not transfer the TMR3 value to the capture register, protecting the previous unread capture value. When the user reads both the high and the low bytes (in any order) of the Capture register, the master overflow bit is transferred to the slave overflow bit (CAxOVF) and then the master bit is reset. The user can then read TCONx to determine the value of CAxOVF. An example of an instruction sequence to read capture registers and capture overflow flag bits is shown in Example 13-1. Depending on the capture source, dif- ferent registers will need to be read. EXAMPLE 13-1: SEQUENCE TO READ CAPTURE REGISTERS TABLE 13-6: REGISTERS ASSOCIATED WITH CAPTURE MOVLB 3 ; Select Bank 3 MOVPF CA2L, LO_BYTE ; Read Capture2 low byte, store in LO_BYTE MOVPF CA2H, HI_BYTE ; Read Capture2 high byte, store in HI_BYTE MOVPF TCON2, STAT_VAL ; Read TCON2 into file STAT_VAL Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR MCLR, WDT 16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000 12h, Bank 2 TMR3L Holding register for the low byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu 13h, Bank 2 TMR3H Holding register for the high byte of the 16-bit TMR3 register xxxx xxxx uuuu uuuu 16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010 17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000 10h, Bank 4 PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010 11h, Bank 4 PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000 07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000 06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu 16h, Bank 2 PR3L/CA1L Timer3 period register, low byte/capture1 register, low byte xxxx xxxx uuuu uuuu 17h, Bank 2 PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte xxxx xxxx uuuu uuuu 14h, Bank 3 CA2L Capture2 low byte xxxx xxxx uuuu uuuu 15h, Bank 3 CA2H Capture2 high byte xxxx xxxx uuuu uuuu 12h, Bank 7 CA3L Capture3 low byte xxxx xxxx uuuu uuuu 13h, Bank 7 CA3H Capture3 high byte xxxx xxxx uuuu uuuu 14h, Bank 7 CA4L Capture4 low byte xxxx xxxx uuuu uuuu 15h, Bank 7 CA4H Capture4 high byte xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by Capture. |
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