RM0319 datasheet(283/368 Pages) STMICROELECTRONICS

283 / 368 page

RM0319

LCD display controller (CLCD)

Doc ID 022640 Rev 3

283/368

24.7

Programming examples

LCD powering up and down

The CLCD requires the following power up sequence to be performed:

●

Vdd is simultaneously applied to the SoC that contains the CLCD peripheral and panel

display driver logic. The following signals are held LOW:

–CLLP

–CLCP

–CLFP

–CLAC

–

CLD[23:0]

–CLLE

●

When Vdd is stabilized, a logic ‘1’ is written to the LcdEn bit in the LCDControl

–CLLP

–CLCP

–CLFP

–CLAC

–CLLE

The CLD[23:0] signals remain low.

●

When the signals in step 2 have stabilized, where appropriate, the contrast voltage Vee

(not controlled or supplied by the CLCD) is then applied.

●

If required, you can use a software timer routine to provide the minimum display

specific delay time between application of the control signals and power to the panel

display. On completion of the software timer routine, power is applied to the panel by

writing a logic ‘1’ to the LcdPwr bit in the LcdControl Register that, in turn, sets the

CLPOWER signal HIGH and enables the CLD[23:0] signals into their active states.

Normally, CLPOWER is used to gate the power to the LCD panel.

The power-down sequence is the reverse of the above four stages and you must follow it

strictly, this time, writing the respective register bits with logic ‘0’.

The power up and power down sequences are shown in Figure 98: Powering up and down

sequences

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