RM0319 datasheet(223/368 Pages) STMICROELECTRONICS

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RM0319

Asynchronous serial ports (UART)

Doc ID 022640 Rev 3

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16.5

Operation

16.5.1

UART hardware flow control

The hardware flow control feature is fully selectable, and enables you to control the serial

data flow by using the nUARTRTS output and nUARTCTS input signals. Figure 80 shows an

example of how two devices can communicate using hardware flow control.

Figure 80.

Hardware flow control between two similar devices

When the RTS flow control is enabled, the nUARTRTS signal is asserted until the receive

FIFO is filled up to the programmed watermark level. When the CTS flow control is enabled,

the transmitter can only transmit data when the nUARTCTS signal is asserted.

The hardware flow control is selectable through bits 14 (RTSEn) and 15 (CTSEn) of the

UART control register (UARTCR). Table 64 lists how bits must be set to enable RTS and

CTS flow control both simultaneously, and independently.

When RTS flow control is enabled, the software cannot control the nUARTRTS line through

bit 11 of the UART control register.

RTS flow control

The RTS flow control logic is linked to the programmable receive FIFO watermark levels.

When RTS flow control is enabled, the nUARTRTS is asserted until the receive FIFO is filled

up to the watermark level. When the receive FIFO watermark level is reached, the

nUARTRTS signal is deasserted, indicating that there is no more room to receive any more

data. The transmission of data is expected to cease after the current character has been

transmitted.

Table 64.

Control bits to enable and disable hardware flow control

UARTCR bit 15

(CTSEn)

UARTCR bit 14

(RTSEn)

Description

Both RTS and CTS flow control enabled

Only CTS flow control enabled

Only RTS flow control enabled

Both RTS and CTS flow control disabled

RX FIFO

UARTRTS

RX FIFO

and

flow control

RX FIFO

and

flow control

nUARTRTS

TX FIFO

and

flow control

TX FIFO

and

flow control

nUARTCTS

flow control

UART 1

UART 2

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