RM0319 datasheet(214/368 Pages) STMICROELECTRONICS

214 / 368 page

Controller area network ports (CAN)

RM0319

214/368

Doc ID 022640 Rev 3

Figure 78.

Structure of the CAN Core protocol controller

The data in the bit timing registers are the configuration input of the CAN protocol controller.

The Baud Rate Prescaler (configured by BRP) defines the length of the time quantum, the

basic time unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and

SJW) defines the number of time quanta in the bit time.

The processing of the bit time, the calculation of the position of the Sample Point, and

occasional synchronisations are controlled by the BTL state machine, which is evaluated

once each time quantum. The rest of the CAN protocol controller, the Bit Stream Processor

(BSP) state machine is evaluated once each bit time, at the Sample Point.

The Shift register serializes the messages to be sent and parallelizes received messages.

Its loading and shifting is controlled by the BSP.

The BSP translates messages into frames and vice versa. It generates and discards the

enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC

code, performs the error management, and decides which type of synchronisation is to be

used. It is evaluated at the Sample Point and processes the sampled bus input bit. The time

after the Sample point that is needed to calculate the next bit to be sent (e.g. data bit, CRC

bit, stuff bit, error flag, or idle) is called the Information Processing Time (IPT).

The IPT is application specific but may not be longer than 2 tq; the CAN IPT is 0 tq. Its

length is the lower limit of the programmed length of Phase_Seg2. In case of a

synchronisation, Phase_Seg2 may be shortened to a value less than IPT, which does not

affect bus timing.

Calculating the bit timing parameters

Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.

The resulting bit time (1/bit rate) must be an integer multiple of the system clock period.

System_Clock

Baudrate

Prescaler

Bit

Timing

Logic

Bit

Stream

Processor

Shift-Register

Receive_Data

Transmit_Data

Control

Status

Received_Data_Bit

Send Message

Received_Message

Next_Data_Bit

Control

Configuration (BRP)

Scaled_Clock (Tq)

Sample_Point

Sampled_Bit

Sync_Mode

Bit_2_Send

Bus_Off

Configuration (TSEG1, TSEG2, SJW)

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