RM0319 datasheet(215/368 Pages) STMICROELECTRONICS

215 / 368 page

RM0319

Controller area network ports (CAN)

Doc ID 022640 Rev 3

215/368

The bit time may consist of 4 to 25 time quanta, the length of the time quantum tq is defined

by the baud rate prescaler with tq = (Baud Rate Prescaler)/fsys. Several combinations may

lead to the desired bit time, allowing iterations of the following steps.

First part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times

measured in the system. A maximum bus length as well as a maximum node delay has to

be defined for expandible CAN bus systems. The resulting time for Prop_Seg is converted

into time quanta (rounded up to the nearest integer multiple of tq).

The Sync_Seg is 1 tq long (fixed), leaving (bit time – Prop_Seg – 1) tq for the two Phase

Buffer Segments. If the number of remaining tq is even, the Phase Buffer Segments have

the same length, Phase_Seg2 = Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.

The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may

not be shorter than the CAN controller’s information processing time, which is, depending on

the actual implementation, in the range of [0..2] tq.

The length of the synchronisation jump width is set to its maximum value, which is the

minimum of 4 and Phase_Seg1.

The oscillator tolerance range necessary for the resulting configuration is calculated by the

formulas given in Oscillator tolerance range section.

If more than one configuration is possible, that configuration allowing the highest oscillator

tolerance range should be chosen.

CAN nodes with different system clocks require different configurations to come to the same

bit rate. The calculation of the propagation time in the CAN network, based on the nodes

with the longest delay times, is done once for the whole network.

The CAN system’s oscillator tolerance range is limited by that node with the lowest tolerance

range.

The calculation may show that bus length or bit rate have to be decreased or that the

oscillator frequencies’ stability has to be increased in order to find a protocol compliant

configuration of the CAN bit timing.

The resulting configuration is written into the Bit Timing register:

(Phase_Seg2-1)&(Phase_Seg1+Prop_Seg-1)&(SynchronisationJumpWidth-1)&(Prescaler-

Example for Bit Timing at high Baudrate

In this example, the frequency of CAN_CLK is 10 MHz, BRP is 0, the bit rate is 1 MBit/s.

100

tCAN_CLK

delay of bus driver

delay of receiver circuit

delay of bus line (40m)

220

tProp

600

6 * tq

tSJW

100

1 * tq

tTSeg1

700

tProp + tSJW

tTSeg2

200

Information Processing Time + 1 * tq

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