RM0319 datasheet(212/368 Pages) STMICROELECTRONICS

212 / 368 page

Controller area network ports (CAN)

RM0319

212/368

Doc ID 022640 Rev 3

same as it would have been from the Sync_Seg to the sample point if no edge had

occurred. The phase error of this “late” edge is less than SJW, so it is fully compensated and

the edge from dominant to recessive at the end of the bit, which is one nominal bit time long,

occurs in the Sync_Seg.

In the second example, an edge from recessive to dominant occurs during Phase_Seg2.

The edge is “early” since it occurs before a Sync_Seg. Reacting to the “early” edge,

Phase_Seg2 is shortened and Sync_Seg is omitted, so that the distance from the edge to

the Sample Point is the same as it would have been from an Sync_Seg to the Sample Point

if no edge had occurred. As in the previous example, the magnitude of this “early” edge

phase error is less than SJW, so it is fully compensated.

The phase buffer segments are lengthened or shortened temporarily only; at the next bit

time, the segments return to their nominal programmed values.

In these examples, the bit timing is seen from the point of view of the CAN implementation’s

state machine, where the bit time starts and ends at the sample points. The state machine

omits Sync_Seg when synchronising on an “early” edge because it cannot subsequently

redefine that time quantum of Phase_Seg2 where the edge occurs to be the Sync_Seg.

The examples in Figure 77 show how short dominant noise spikes are filtered by

synchronisations. In both examples, the spike starts at the end of Prop_Seg and has the

length of (Prop_Seg + Phase_Seg1).

In the first example, the synchronisation jump width is greater than or equal to the phase

error of the spike edge from recessive to dominant. Therefore, the sample point is shifted

after the end of the spike; a recessive bus level is sampled.

In the second example, SJW is shorter than the phase error, so the sample point cannot be

shifted far enough; the dominant spike is sampled as actual bus level.

Figure 77.

Filtering of short dominant spikes

Rx-Input

Spike

Recessive

dominant

Sample Point

Phase_Seg2

Sync_Seg

Prop_Seg

Phase_Seg1

Sample Point

Rx-Input

Spike

Recessive

dominant

SJW > Phase Error

SJW < Phase Error

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