RM0319 datasheet(210/368 Pages) STMICROELECTRONICS

210 / 368 page

Controller area network ports (CAN)

RM0319

210/368

Doc ID 022640 Rev 3

timing segments are shifted with regard to A. Node B sends an identifier with higher priority

and so it will win the arbitration at a specific identifier bit when it transmits a dominant bit

while node A transmits a recessive bit. The dominant bit transmitted by node B will arrive at

node A after the delay(B_to_A).

Due to oscillator tolerances, the actual position of node A’s sample point can be anywhere

inside the nominal range of node A’s phase buffer segments, so the bit transmitted by node

B must arrive at node A before the start of Phase_Seg1. This condition defines the length of

Prop_Seg.

If the edge from recessive to dominant transmitted by node B would arrive at node A after

the start of Phase_Seg1, it could happen that node A samples a recessive bit instead of a

dominant bit, resulting in a bit error and the destruction of the current frame by an error flag.

The error occurs only when two nodes arbitrate for the CAN bus that have oscillators of

opposite ends of the tolerance range and that are separated by a long bus line; this is an

example of a minor error in the bit timing configuration (Prop_Seg to short) that causes

sporadic bus errors.

Some CAN implementations provide an optional 3 Sample Mode The CAN does not. In this

mode, the CAN bus input signal passes a digital low-pass filter, using three samples and a

majority logic to determine the valid bit value. This results in an additional input delay of 1 tq,

requiring a longer Prop_Seg.

Phase buffer segments and synchronisation

The phase buffer segments (Phase_Seg1 and Phase_Seg2) and the synchronisation jump

width (SJW) are used to compensate for the oscillator tolerance. The phase buffer segments

may be lengthened or shortened by synchronisation.

Synchronisations occur on edges from recessive to dominant, their purpose is to control the

distance between edges and sample points.

Edges are detected by sampling the actual bus level in each time quantum and comparing it

with the bus level at the previous Sample Point. A synchronisation may be done only if a

recessive bit was sampled at the previous Sample Point and if the actual time quantum’s bus

level is dominant.

An edge is synchronous if it occurs inside of Sync_Seg, otherwise the distance between

edge and the end of Sync_Seg is the edge phase error, measured in time quanta. If the

edge occurs before Sync_Seg, the phase error is negative, else it is positive.

Two types of synchronisation exist: hard synchronisation and resynchronisation.

A hard synchronisation is done once at the start of a frame; inside a frame only

resynchronisations occur.

●

Hard synchronisation

After a hard synchronisation, the bit time is restarted with the end of Sync_Seg, regardless

of the edge phase error. Thus hard synchronisation forces the edge which has caused the

hard synchronisation to lie within the synchronisation segment of the restarted bit time.

●

Bit resynchronisation

Resynchronisation leads to a shortening or lengthening of the bit time such that the position

of the sample point is shifted with regard to the edge.

When the phase error of the edge which causes resynchronisation is positive, Phase_Seg1

is lengthened. If the magnitude of the phase error is less than SJW, Phase_Seg1 is

lengthened by the magnitude of the phase error, else it is lengthened by SJW.

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