RM0319 datasheet(207/368 Pages) STMICROELECTRONICS

207 / 368 page

RM0319

Controller area network ports (CAN)

Doc ID 022640 Rev 3

207/368

15.4.18

Handling interrupts

If several interrupts are pending, the CAN Interrupt register will point to the pending interrupt

with the highest priority, disregarding their chronological order. An interrupt remains pending

until the CPU has cleared it.

The Status Interrupt has the highest priority. Among the message interrupts, the interrupt

priority of the message object decreases as the message number increases.

A message interrupt is cleared by clearing the message object IntPnd bit. The Status

Interrupt is cleared by reading the Status register.

The interrupt identifier IntId in the Interrupt register indicates the cause of the interrupt.

When no interrupt is pending, the register will hold the value zero. If the value of the

Interrupt register is different from zero, then there is an interrupt pending and, if IE is set, the

interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until the

Interrupt register is back to value zero (the cause of the interrupt is reset) or until IE is reset.

The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated

(not necessarily changed) the Status register (Error Interrupt or Status Interrupt). This

interrupt has the highest priority. The CPU can update (reset) the status bits RxOk, TxOk

and LEC, but a write access of the CPU to the Status register can never generate or reset

an interrupt.

All other values indicate that the source of the interrupt is one of the message objects, IntId

points to the pending message interrupt with the highest interrupt priority.

The CPU controls whether a change of the Status register may cause an interrupt (bits EIE

and SIE in the CAN Control register) and whether the interrupt line becomes active when

the Interrupt register is different from zero (bit IE in the CAN Control register). The Interrupt

The CPU has two possibilities to follow the source of a message interrupt. First, it can follow

the IntId in the Interrupt register and, second, it can poll the Interrupt Pending register.

An interrupt service routine reading the message that is the source of the interrupt may read

the message and reset the message object’s IntPnd at the same time (bit ClrIntPnd in the

Command Mask register). When IntPnd is cleared, the Interrupt register will point to the next

message object with a pending interrupt.

15.4.19

Configuring the bit timing

Even if minor errors in the configuration of the CAN bit timing do not result in immediate

failure, the performance of a CAN network can be reduced significantly.

In many cases, the CAN bit synchronisation will amend a faulty configuration of the CAN bit

timing to such a degree that only occasionally an error frame is generated. In the case of

arbitration, however, when two or more CAN nodes simultaneously try to transmit a frame, a

misplaced sample point may cause one of the transmitters to become error passive.

The analysis of such sporadic errors requires a detailed knowledge of the CAN bit

synchronisation inside a CAN node and the interaction of the CAN nodes on the CAN bus.

Bit time and time rate

CAN supports bit rates in the range of lower than 1 kBit/s up to 1000 kBit/s. Each member of

the CAN network has its own clock generator, usually a quartz oscillator. The timing

parameter of the bit time (for instance, the reciprocal of the bit rate) can be configured

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