RM0319 datasheet(124/368 Pages) STMICROELECTRONICS

124 / 368 page

USB 2.0 Device ports (UDC)

RM0319

124/368

Doc ID 022640 Rev 3

11.3.12

AHB interface

This block contains all the subsystem’s AHB protocol logic. In particular, the AHB interface

has two functional states where it is able to act:

●

As an AHB slave, when the application programs the CSRs of either the UDC-AHB

Subsystem or the UDC (Section 11.3.8),

●

As an AHB master, when the DMA performs data transfers.

Acting as AHB master, the UDC-AHB subsystem accesses the application memory for

descriptors and data buffers. When the subsystem is in slave-only mode, the AHB interface

also acts as a slave. In this mode, all the FIFOs are memory-mapped, and the application

writes directly to the FIFOs.

11.3.13

CSRs slave access

The CSRs slave access block is active in DMA mode only (Section 11.4.1: DMA mode) and,

acting as an AHB slave, it responds to any CSRs access from the application (which acts as

an AHB master).

In DMA mode CSR registers are accessible through CSR slave access block as this time

AHB slave only block is de-activated. This AHB slave only block is activated only in slave

mode.

11.4

Operation

The UDC-AHB Subsystem supports two distinct operation modes:

●

DMA mode (detailed in Section 11.4.1), a DMA-based implementation where the UDC-

AHB Subsystem acts as an AHB master for data transfers.

●

Slave-only mode (detailed in Section 11.4.2), where the UDC-AHB Subsystem is

slaved to the application and any application AHB master reads data from, or writes

data to the memory-mapped FIFOs provided by the device.

In both modes, all data transfers are interrupt-driven.

11.4.1

DMA mode

In general, a major advantage of DMA-based implementations is that they spare the main

processor’s computing power from involvement in data transfer tasks. Moreover, use of a

scatter-gather DMA helps applications to make efficient and optimal use of system memory,

which is indeed a major design constraint on portable systems.

Specifically, in DMA mode, the UDC-AHB subsystem implements a true scatter-gather

memory distribution, in which memory structures are scattered over the system memory. As

illustrated in Figure 36, each in/out endpoint memory structure is implemented as a linked-

list, where each element of the list is a data buffer of a predefined size.

In addition to data (both in and out), each buffer also has a status quadlet and a pointer to

the next buffer. The last element of such a linked list can point either to a null pointer or, if

the linked list is implemented as a ring buffer, to the first element of the list. Data buffer

structure for both in and out endpoint is described in RM0321: SPEAr320S address map

and registers reference manual.

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