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RM0319 датащи(PDF) 125 Page - STMicroelectronics

номер детали RM0319
подробное описание детали  SPEAr320S architecture and functionality
PDF  368 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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RM0319 датащи(HTML) 125 Page - STMicroelectronics

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RM0319
USB 2.0 Device ports (UDC)
Doc ID 022640 Rev 3
125/368
Besides, all control endpoints implement an additional 16-byte buffer to store SETUP data.
The SETUP data structure (detailed in RM0321: SPEAr320S address map and registers)
does not implement a linked-list structure.
Figure 36.
Linked-list memory structure in DMA mode
In DMA mode, before starting any action, the application must both initialize the buffer
descriptor chains in the DMA data memory structure for all active endpoints of the UDC-
AHB subsystem, and configure the required CSRs during the USB reset.
A brief description of both in and out operation in DMA mode.
11.4.2
In operation (Data transfer To USB Host)
If the UDC-AHB subsystem receives an in token from a USB Host for a non-isochronous
endpoint (such as, bulk, interrupt or control), it checks the corresponding TxFIFO for data
availability. If data is available, the TxFIFO is read and the data is provided to the UDC for
transfer to USB Host. In contrast, if the TxFIFO is empty (no data), the UDC-AHB
subsystem sends an interrupt to the application and the UDC sends a NAK handshake to
the USB Host connected to that endpoint.
On receiving the interrupt, at first the application probes the endpoint interrupt register, to
determine which endpoint has requested the interrupt. Having determined this endpoint,
then the application probes the endpoint status register, to determine the interrupt’s cause.
Upon notification that this is an in token for a particular endpoint, the application updates the
addressed endpoint’s system memory buffer with data. Besides, the application reports to
the DMA the availability of such data by setting the poll demand bit in the subsystem’s
CSRs.
Note:
Each endpoint has a dedicated poll demand bit within CSRs, specifically in the endpoint-
specific endpoint control register.
Setup Buffer
Pointer
IN Data Descriptor
Pointer
Setup buffer Status Quadlet
In buffer Status Quadlet
In buffer Status Quadlet
In buffer Status Quadlet
Data
R
R
R
R
Data
Next Pointer
Next Pointer
Next Pointer
Buffer
Buffer
Buffer
OUT Data
Descriptor Pointer
OUT buffer Status Quadlet
OUT buffer Status Quadlet
OUT buffer Status Quadlet
R
R
R
Next Pointer
Next Pointer
Next Pointer
Buffer
Buffer
Buffer



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