RM0319 datasheet(120/368 Pages) STMICROELECTRONICS

120 / 368 page

USB 2.0 Device ports (UDC)

RM0319

120/368

Doc ID 022640 Rev 3

11.3.3

SOF tracker

The USB Host sends start-of-frame (SOF) packets to USB 2.0 device every 1 ms for full-

speed (FS) operation, and every 125 µs for high-speed (HS) operation. Each SOF token

represents the start of every frame (for FS) or micro-frame (for HS) respectively, in case of

isochronous (ISO) data synchronization.

The start-of-frame (SOF) tracker block within the UDC-AHB subsystem is intended to track

any incoming SOF packets from the USB Host. With this aim, the SOF tracker runs internal

frame counters according to the operation rate (that is, 1 ms for FS and 125 µs for HS).

When a SOF packet is received from the USB Host, the UDC gets the 11 bit frame number

from the packet, and gives it to the back end within a single clock pulse, indicating the

reception of a SOF token.

In contrast, if a missing SOF packet is detected, the SOF tracker generates an event that is

used by the ISO in FIFOs to clear residual data from the previous frame, whereas UDC-AHB

subsystem moves to the next frame to provide synchronization.

In order to provide backward-compatibility with the FS 1 ms frame of USB 1.1, in HS mode

the frame number is incremented by UDC once every eight 125 µs micro-frames only. As a

consequence, the SOF tracker module generates the correct 14 bit micro-frame number by

adding a 3 bit micro-frame counter (operated by the SOF tracker itself) to the 11 bit frame

number provided by the UDC.

11.3.4

Receive FIFO controller

All out endpoints (dedicated to transactions coming from the USB Host) share a common

receive FIFO (RxFIFO), which is managed by multiple receive FIFO controller. In particular,

the RxFIFO provides the UTLI with enough space to either accept the incoming packet from

the USB Host or send a NYET (UDC20 only) or a NAK handshake packet.

In particular, the RxFIFO consists of two individual FIFOs, one for the data and one for the

addresses. As depicted in Figure 35, the data FIFO is implemented as RAM, whereas the

address FIFO is implemented using registers. Each 32 bit wide entry in the address FIFO

corresponds to a received out packet, and it is associated to both the destination endpoint

number and a flag to distinguish regular data from the 8 bytes of SETUP data.

Note:

The total data FIFO size is 4KB. Out of the 37-bit wide data 32 bits are OUT/IN data and the

remaining 5 bits are status information. The maximum depth of the address RxFIFO is 4,

hence at a given time a maximum of 4 OUT packets can be accommodated simultaneously.

The depth of the data RXFIFO is limited to 2KB. So during simultaneous storing of 4 OUT

packets, each packet can not be more than 512 bytes. But if OUT packets are 1024 bytes in

size (maximum size) then only two OUT packets can be accommodated. Hence number of

OUT packets that can be accommodated is limited by the size of the OUT packets. The rest

of the data FIFO, for instance 2 KB (out of total of 4KB data FIFO) is used for TxFIFO.

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