RM0319 datasheet(122/368 Pages) STMICROELECTRONICS

122 / 368 page

USB 2.0 Device ports (UDC)

RM0319

122/368

Doc ID 022640 Rev 3

11.3.5

Endpoints

11.3.6

Endpoint FIFO controller (Transmit FIFO controller)

An endpoint FIFO controller block manages the FIFO of a specific in endpoint (dedicated to

transactions to the USB Host) supported by the UDC-AHB subsystem. In particular, each in

endpoint is associated to a Transmit FIFO (TxFIFO) which is mapped in external RAM, and

each TxFIFO is in charge of an endpoint FIFO controller.

Each endpoint FIFO controller maintains the write and read pointers to access the memory

where relevant TxFIFO is located. Besides, these controllers need both the base address

and the buffer size of each endpoint TxFIFO to implement adaptive buffer management.

This feature allows to tailor the size of each TxFIFO depending on specific buffering

requirements.

In particular, the base address of each TxFIFO results from the upper limit of the previous

TxFIFO which, in turn, depends on the buffer size set by the CSRs for this endpoint

(Endpoint buffer size and received packet frame number register). That is, the base address

of the TxFIFO associated to nth in endoint added to the size of the TxFIFO of the same nth in

endpoint represents the base address for the TxFIFO associated to the (n+1)th in endpoint.

Note:

Any attempt to read from TxFIFO via the AHB interface results in an AHB error.

Like receive FIFO controller, the transmit endpoint FIFO controller also requires a

confirmation signal indicating a successful transfer to TxFIFO. This confirmation signal

allows the controller to export the FIFO pointers to other domains.

11.3.7

Control and status registers

The control and status registers (CSRs) allow to exchange control information with the

application, as well as provide a means for the application to control the UDC-AHB

subsystem.

11.3.8

AHB slave-only interface

The AHB slave-only interface block is active only when the UDC-AHB subsystem is

configured as a slave on the AHB.

Table 36.

Endpoints assignment

Endpoint number

Endpoint direction

Transfer type

IN/OUT

Control.

1-3-5-7-9-11-13-15

Software configurable to:

Bulk

Interrupt

Isochronous.

2-4-6-8-10-12-14

OUT

Software configurable to:

Bulk

Interrupt

Isochronous.

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