RM0319 datasheet(117/368 Pages) STMICROELECTRONICS

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RM0319

USB 2.0 Device ports (UDC)

Doc ID 022640 Rev 3

117/368

USB 2.0 Device ports (UDC)

This chapter focuses on USB Device functionality and operation.

For technical details about the programmable registers related to the USB Device, refer to

the USB Device registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

11.1

Overview

In addition to single independent USB 2.0 Hosts, SPEAr320S provides a USB 2.0 Device

which is fully compliant with the Universal Serial Bus Specification (version 2.0), offering an

interface to the industry-standard AHB bus.

11.2

Main features

●

A PHY interface implementing a USB 2.0 transceiver macrocell interface (UTMI) fully

compliant with UTMI specification (version 1.05), to execute serialization and

deserialization of transmissions over the USB line.

●

Unidirectional/bidirectional 8-/16 bit UTMI data bus interfaces are supported.

●

A USB plug detect (UPD) which detects the connection of a device (detailed in

Section 11.4.7).

●

A USB Device controller (UDC) which is connected to the AHB bus and generates the

commands for the UTMI PHY. Hereafter the UDC along with AHB interface is referred

to UDC-AHB subsystem.

●

The UDC-AHB supports the 480 Mbps high-speed (HS) for USB 2.0, as well as the 12

Mbps full-speed (FS) for USB 1.1.

●

The UDC-AHB supports 16 physical endpoints (listed in Table 36), and proper

configurations to achieve logical endpoints.

●

Both DMA mode and slave-only mode supported (detailed in Section 11.4).

●

In DMA mode, the UDC-AHB supports descriptor-based memory structures in

application memory.

●

In both modes, an AHB slave is provided by UDC-AHB, acting as programming

interface to access to memory-mapped control and status registers (CSRs).

●

An AHB master for data transfer to system memory, supporting 8, 16, and 32 bit wide

data transactions on the AHB bus.

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