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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0056 датащи(PDF) 122 Page - STMicroelectronics |
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PM0056 датащи(HTML) 122 Page - STMicroelectronics |
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122 / 156 page  Core peripherals PM0056 122/156 DocID15491 Rev 5 4.3.4 Interrupt set-pending registers (NVIC_ISPRx) Address offset: 0x00 - 0x0B Reset value: 0x0000 0000 Required privilege: Privileged The ISPR0-ISPR2 registers force interrupts into the pending state, and show which interrupts are pending. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 SETPEND[31:16] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 15 14 13 12 11 10 9 8 76 54 3 21 0 SETPEND[15:0] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs Bits 31:0 SETPEND[31:0]: Interrupt set-pending bits Write: 0: No effect 1: Changes interrupt state to pending Read: 0: Interrupt is not pending 1: Interrupt is pending See Table 41: Mapping of interrupts to the interrupt variables on page 119 for the correspondence of interrupts to each register bit. Writing 1 to the ISPR bit corresponding to an interrupt that is pending: –has no effect. Writing 1 to the ISPR bit corresponding to a disabled interrupt: – sets the state of that interrupt to pending. |
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