PM0056 datasheet(59/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Specific example 2: Compare and update value shows the use of conditional instructions to

update the value of R4 if the signed value R0 and R2 are greater than R1 and R3 respectively.

Specific example 2: Compare and update value

CMP R0, R1 ; compare R0 and R1, setting flags

ITT GT ; IT instruction for the two GT conditions

CMPGT R2, R3; if 'greater than', compare R2 and R3, setting flags

MOVGT R4, R5 ; if still 'greater than', do R4 = R5

3.3.8

Instruction width selection

There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding

depending on the operands and destination register specified. For some of these

instructions, you can force a specific instruction size by using an instruction width suffix.

The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction

encoding.

If you specify an instruction width suffix and the assembler cannot generate an instruction

encoding of the requested width, it generates an error.

In some cases it might be necessary to specify the .W suffix, for example if the operand is

the label of an instruction or literal data, as in the case of branch instructions. This is

because the assembler might not automatically generate the right size encoding.

To use an instruction width suffix, place it immediately after the instruction mnemonic and

condition code, if any. Specific example 3: Instruction width selection shows instructions

with the instruction width suffix.

Specific example 3: Instruction width selection

BCS.W label; creates a 32-bit instruction even for a short branch

ADDS.W R0, R0, R1; creates a 32-bit instruction even though the same

; operation can be done by a 16-bit instruction

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