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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0056 датащи(PDF) 118 Page - STMicroelectronics |
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PM0056 датащи(HTML) 118 Page - STMicroelectronics |
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118 / 156 page  Core peripherals PM0056 118/156 DocID15491 Rev 5 4.3 Nested vectored interrupt controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • up to 81 interrupts (depends on the STM32 device type, refer to the datasheets) • A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority • Level and pulse detection of interrupt signals • Dynamic reprioritization of interrupts • Grouping of priority values into group priority and subpriority fields • Interrupt tail-chaining • An external Non-maskable interrupt (NMI) 0x10 MPU_RASR Res. AP[2:0] TEX [2:0] S C B SRD[7:0] SIZE Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 0x14 MPU_RBAR_ A1(1) ADDR[31:N]... REGION [3:0] Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 0x18 MPU_RASR_ A1(2) Res. AP[2:0] TEX [2:0] S C B SRD[7:0] SIZE Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 0x1C MPU_RBAR_ A2(1) ADDR[31:N]... REGION [3:0] Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 0x20 MPU_RASR_ A2(2) Res. AP[2:0] TEX [2:0] S C B SRD[7:0] SIZE Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 0x1C MPU_RBAR_ A3(1) ADDR[31:N]... REGION [3:0] Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 0x20 MPU_RASR_ A3(2) Res. AP[2:0] TEX [2:0] S C B SRD[7:0] SIZE Reset Value 0 0 000 0 0 0 000 000 000000 000000 00 0 0 0 0 1. Alias of MPU_RBAR register 2. Alias of MPU_RASR register Table 40. MPU register map and reset values (continued) Offset Register |
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