PM0056 datasheet(119/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

The processor automatically stacks its state on exception entry and unstacks this state on

exception exit, with no instruction overhead. This provides low latency exception handling.

The hardware implementation of the NVIC registers is:

4.3.1

The CMSIS mapping of the Cortex-M3 NVIC registers

To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the

CMSIS:

•

The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers

map to arrays of 32-bit integers, so that:

–

The array ISER[0] to ISER[2] corresponds to the registers ISER0-ISER2

–

The array ICER[0] to ICER[2] corresponds to the registers ICER0-ICER2

–

The array ISPR[0] to ISPR[2] corresponds to the registers ISPR0-ISPR2

–

The array ICPR[0] to ICPR[2] corresponds to the registers ICPR0-ICPR2

–

The array IABR[0] to IABR[2] corresponds to the registers IABR0-IABR2.

•

The 8-bit fields of the Interrupt Priority Registers map to an array of 8-bit integers, so

that the array IP[0] to IP[67] corresponds to the registers IPR0-IPR67, and the array

entry IP[n] holds the interrupt priority for interrupt n.

The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority

Registers. For more information see the description of the NVIC_SetPriority function in

NVIC programming hints on page 127. Table 41 shows how the interrupts, or IRQ numbers,

map onto the interrupt registers and corresponding CMSIS variables that have one bit per

interrupt.

Table 41. Mapping of interrupts to the interrupt variables

Interrupts

CMSIS array elements(1)

1. Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds

to the ICER1 register.

Set-enable

Clear-enable

Set-pending

Clear-pending

Active Bit

0-31

ISER[0]

ICER[0]

ISPR[0]

ICPR[0]

IABR[0]

32-63

ISER[1]

ICER[1]

ISPR[1]

ICPR[1]

IABR[1]

64-67

ISER[2]

ICER[2]

ISPR[2]

ICPR[2]

IABR[2]

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