PM0056 datasheet(80/156 Pages) STMICROELECTRONICS

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The Cortex-M3 instruction set

PM0056

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DocID15491 Rev 5

Restrictions

You can use SP and PC only in the MOV instruction, with the following restrictions:

•

The second operand must be a register without shift

•

You must not specify the S suffix

When Rd is PC in a MOV instruction:

•

bit[0] of the value written to the PC is ignored

•

A branch occurs to the address created by forcing bit[0] of that value to 0.

Note:

Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use

of a BX or BLX instruction to branch for software portability to the ARM instruction set.

Condition flags

If S is specified, these instructions:

•

Update the N and Z flags according to the result

•

Can update the C flag during the calculation of operand2 (see Flexible second operand

on page 52).

•

Do not affect the V flag

Example

MOVSR11, #0x000B; write value of 0x000B to R11, flags get updated

MOVR1, #0xFA05; write value of 0xFA05 to R1, flags are not updated

MOVSR10, R12; write value in R12 to R10, flags get updated

MOVR3, #23; write value of 23 to R3

MOVR8, SP; write value of stack pointer to R8

MVNSR2, #0xF; write value of 0xFFFFFFF0 (bitwise inverse of 0xF)

; to the R2 and update flags

3.5.7

MOVT

Move top.

Syntax

MOVT{cond} Rd, #imm16

where:

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rd’ is the destination register

•

‘imm16’ is a 16-bit immediate constant

Operation

MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its

destination register. The write does not affect Rd[15:0].

The MOV, MOVT instruction pair enables you to generate any 32-bit constant.

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