PM0056 datasheet(81/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Restrictions

Rd must be neither SP nor PC.

Condition flags

This instruction does not change the flags.

Examples

MOVTR3, #0xF123; write 0xF123 to upper halfword of R3, lower halfword

; and APSR are unchanged

3.5.8

REV, REV16, REVSH, and RBIT

Reverse bytes and reverse bits.

Syntax

op{cond} Rd, Rn

where:

•

‘op’ is one of:

REV: Reverse byte order in a word

REV16: Reverse byte order in each halfword independently

REVSH: Reverse byte order in the bottom halfword, and sign extends to 32 bits

RBIT: Reverse the bit order in a 32-bit word

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rd’ is the destination register

•

‘Rn’ is the register holding the operand

Operation

Use these instructions to change endianness of data:

•

REV: Converts 32-bit big-endian data into little-endian data or 32-bit little-endian data

into big-endian data.

•

REV16: Converts 16-bit big-endian data into little-endian data or 16-bit little-endian data

into big-endian data.

•

REVSH: Converts either:

–

16-bit signed big-endian data into 32-bit signed little-endian data

–

16-bit signed little-endian data into 32-bit signed big-endian data

Restrictions

Do not use either SP or PC.

Condition flags

These instructions do not change the flags.

Examples

REVR3, R7; reverse byte order of value in R7 and write it to R3

REV16 R0, R0; reverse byte order of each 16-bit halfword in R0

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