PM0056 datasheet(125/156 Pages) STMICROELECTRONICS

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PM0056

Core peripherals

4.3.7

Interrupt priority registers (NVIC_IPRx)

Address offset: 0x00- 0x0B

Reset value: 0x0000 0000

Required privilege: Privileged

The IPR0-IPR16 registers provide a 4-bit priority field for each interrupt. These registers are

byte-accessible. Each register holds four priority fields, that map to four elements in the

CMSIS interrupt priority array IP[0] to IP[67], as shown in Figure 19.

Figure 19. NVIC__IPRx register mapping

See The CMSIS mapping of the Cortex-M3 NVIC registers on page 119 for more

information about the IP[0] to IP[67] interrupt priority array, that provides the software view

of the interrupt priorities.

Find the IPR number and byte offset for interrupt N as follows:

•

The corresponding IPR number, M, is given by M = N DIV 4

•

The byte offset of the required Priority field in this register is N MOD 4, where:

–

byte offset 0 refers to register bits[7:0]

–

byte offset 1 refers to register bits[15:8]

–

byte offset 2 refers to register bits[23:16]

–

byte offset 3 refers to register bits[31:24].

Table 42. IPR bit assignments

Bits

Name

Function

[31:24]

Priority, byte offset 3

Each priority field holds a priority value, 0-255. The lower the value,

the greater the priority of the corresponding interrupt. The processor

implements only bits[7:4] of each field, bits[3:0] read as zero and

ignore writes.

[23:16]

Priority, byte offset 2

[15:8]

Priority, byte offset 1

[7:0]

Priority, byte offset 0

24 23

16 15

8 7

IP[80 ]

IPR20

IP[4m + 3]

IP[4m + 2]

IP[4m + 1]

IP[4m ]

IPRm

IP[3]

IP[2]

IP[1]

IP[0]

IPR0

Reserved

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