PM0056 datasheet(126/156 Pages) STMICROELECTRONICS

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Core peripherals

PM0056

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DocID15491 Rev 5

4.3.8

Software trigger interrupt register (NVIC_STIR)

Address offset: 0xE00

Reset value: 0x0000 0000

Required privilege: When the USERSETMPEND bit in the SCR is set to 1, unprivileged

software can access the STIR, see Section 4.4.6: System control register (SCB_SCR). Only

privileged software can enable unprivileged access to the STIR.

4.3.9

Level-sensitive and pulse interrupts

STM32 interrupts are both level-sensitive and pulse-sensitive. Pulse interrupts are also

described as edge-triggered interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal.

Typically this happens because the ISR accesses the peripheral, causing it to clear the

interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the

rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral

must assert the interrupt signal for at least one clock cycle, during which the NVIC detects

the pulse and latches the interrupt.

When the processor enters the ISR, it automatically removes the pending state from the

interrupt, see Hardware and software control of interrupts. For a level-sensitive interrupt, if

the signal is not deasserted before the processor returns from the ISR, the interrupt

becomes pending again, and the processor must execute its ISR again. This means that the

peripheral can hold the interrupt signal asserted until it no longer needs servicing.

Hardware and software control of interrupts

The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the

following reasons:

•

The NVIC detects that the interrupt signal is HIGH and the interrupt is not active

•

The NVIC detects a rising edge on the interrupt signal

•

Software writes to the corresponding interrupt set-pending register bit, see

Section 4.3.4: Interrupt set-pending registers (NVIC_ISPRx), or to the STIR to make an

SGI pending, see Section 4.3.8: Software trigger interrupt register (NVIC_STIR).

Reserved

INTID[8:0]

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Bits 31:9

Reserved, must be kept cleared.

Bits 8:0

NTID[8:0] Software generated interrupt ID

Write to the STIR to generate a Software Generated Interrupt (SGI). The value to be written is

the Interrupt ID of the required SGI, in the range 0-239. For example, a value of 0b000000011

specifies interrupt IRQ3.

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