PM0056 datasheet(65/156 Pages) STMICROELECTRONICS

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PM0056

The Cortex-M3 instruction set

Operation

These load and store instructions perform the same function as the memory access

instructions with immediate offset (see LDR and STR, immediate offset on page 61). The

difference is that these instructions have only unprivileged access even when used in

privileged software.

When used in unprivileged software, these instructions behave in exactly the same way as

normal memory access instructions with immediate offset.

Restrictions

In these instructions:

•

Rn must not be PC

•

Rt must be neither SP nor PC.

Condition flags

These instructions do not change the flags.

Examples

STRBTEQR4, [R7]; conditionally store least significant byte in

; R4 to an address in R7, with unprivileged access

LDRHTR2, [R2, #8]; load halfword value from an address equal to

; sum of R2 and 8 into R2, with unprivileged access

3.4.5

LDR, PC-relative

Load register from memory.

Syntax

LDR{type}{cond} Rt, label

LDRD{cond} Rt, Rt2, label; load two words

where:

•

‘type’ is one of the following:

B: Unsigned byte, zero extends to 32 bits

SB: Signed byte, sign extends to 32 bits

H: Unsigned halfword, sign extends to 32 bits

SH: Signed halfword, sign extends to 32 bits

—: Omit, for word

•

‘cond’ is an optional condition code (see Conditional execution on page 57)

•

‘Rt’ is the register to load or store

•

‘Rt2’ is the second register to load or store

•

‘label’ is a PC-relative expression (see PC-relative expressions on page 56)

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